IWLPC (Wafer-Level Packaging) Conference Proceedings


PLASMA STRESS RELIEF TECHNOLOGY

Authors: Ryota Furukawa and Kazuhisa Arai
Company: Panasonic
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: We have developed new plasma stress relief technology. This technology can remove the damaged Silicon wafer layer during the grinding process with low running cost. Furthermore it is an environmentally friendly technology because of the dry process. It can also realize high productivity of 1.5µm/min when etching Silicon. We have chosen Sulphur Hexafluoride plasma to achieve a high Silicon etching rate.

SF6 plasma can etch away Silicon effectively by means of chemical reaction. We can improve not only die shear strength but also die warpage with this technology. The configuration of the chamber we adopted is called narrow gap type which enables plasma to discharge with high pressure. High pressure and narrow gap type plasma discharge can use high density neutral radicals so that realize isotropic etching. This isotropic property is extremely useful when it comes to the dicing before grinding(DBG) process.

In the conventional process we do dicing after the grinding process. In this case chipping and cracking of Silicon wafer could happen on the lateral phase of the die. However we can overcome these problems by means of dicing before grinding plus plasma stress relief process. We can remove the damaged layer of not only the grinding surface but also the side wall of chip lateral surface totally because our plasma system etches isotropically.



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