IWLPC (Wafer-Level Packaging) Conference Proceedings


CHALLENGES AND DEVELOPMENTS IN WAFER LEVEL SOLDER INTERCONNECT

Authors: Thomas Goodman and Peter Elenius
Company: E&G Technology Partners, LLC
Date Published: 10/10/2004   Conference: IWLPC (Wafer-Level Packaging)


Abstract: The use of wafer-level solder interconnect is increasing in a wide range of high-performance and portable applications. In flip-chip mounting, the trend towards finer-pitch bumping will require development and implementation of new structures to handle the higher current densities per bump in devices for high-performance computing.

This is a result of the decreasing cross-sectional area that increases the propensity to electromigration. In addition, finer pitch devices will force the development of more effective chemistries, equipment and processes for under-chip cleaning that is becoming more critical after attachment of the flip chip to a substrate.

There has not been significant expansion of the use of wafer level packaging into new OEM markets, although the penetration within these markets has increased significantly. The most important trend has been for continued cost reductions. Low-cost, robust technologies have been adopted for certain applications but may not fit the bill for all.

In the quest for DRAM market penetration, the development of the Fully Buffered DIMM architecture may have delayed implementation of wafer-level solder interconnect in the high-end server market. How this will affect future implementation in other markets such as costperformance computing is not clear.

Key words: WLP, electromigration, under-chip cleaning, DRAM.



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