WAFER LEVEL MEMS PACKAGING STRATEGIESAuthors: Daniel F. Baldwin, Ph.D.
Company: Georgia Institute of Tech.
Date Published: 10/10/2004 Conference: IWLPC (Wafer-Level Packaging)
Thisphysical interface is exactly what traditional microelectronics packaging attempts to issolate the device from due to inherent sensitivity of the ICs. The net result is large footprint, high cost, high complexity MEMS packaging solutions. These are some of the many reasons wafer level packaging of MEMS is gaining momentum in the industry.
Wafer level packaging (WLP) presents a unique opportunity for the packaging of MEMS devices. It leverages many standard microelectronics packaging techniques and introduces a number of wafer level bonding techniques making it one of the most attractive and cost effective MEMS packaging strategies for emerging microsystems. Like microelectronics versions, wafer level MEMS packaging accomplishes all packaging elements at the wafer level thereby amortizing all the more expensive unit packaging steps over a multitude of devices keeping the net cost low.
Another advantage of WLP is that the package is microsystem dimension resulting in a minimum size and weight packaging solution. WLPs have the advantage of having the smallest possible package footprint, i.e., the same size as the die itself. This means that WLP offers a potential solution for size critical components that are often found in many handheld consumer electronics products. This paper reviews some of the recent advances in WLP of MEMS.
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