BACK END PROCESS DEVELOPMENT FOR WAFER LEVEL CHIP SCALE PACKAGINGAuthor: Pamela Chang
Company: Intarsia Corporation
Date Published: 9/12/1999 Conference: SMTA International
The back-end process we describe includes polymer coating, solder ball placement, laser marking, singulation, testing, and tape & reel. All of these are performed at the wafer level. The polymer coating process is used to define the grid array openings on the packaged devices with 0.3 mm solder balls on 0.5 mm pitch. Laser marking is incorporated with the requirement of producing alphanumeric and two-dimensional cell codes on both silicon and glass wafers. The unique requirement for singulation is to minimize the displacement of bumped die during the dicing and cleaning process. This is to minimize potential misalignment of the die during test. In order to test a diced wafer at the wafer level, we have worked with a vendor to supply a handler that can accept dicing film frames and compensate for die misalignments. Lastly, traditional tape & reel machines are not suitable for bulk packaging of small, wafer level devices. We have purchased a modified die taping/sorting machine and have designed a custom tape pocket.
All versions of the Intarsia wafer level CSP are fully surface-mount compatible and are designed to allow a wide assembly process window with existing placement equipment and technologies. Board level assembly issues unique to CSPs will be also discussed.
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