SMTA International Conference Proceedings


Authors: R. Gorrell, D. Le-Huu, S. Qu, D. Banks, D. Hanson
Company: 3M Company
Date Published: 9/26/2004   Conference: SMTA International

Abstract: High performance integrated circuit chip packages have migrated from peripherally bonded configurations to area array, flip chip configurations. It is not unusual to have total die I/O of more than 4000 pins on a 200µm pitch in leading edge applications. Next generation groundrules require a substrate technology with less than 200µm full array pitch with a path to even tighter pitches.

Simultaneously, market conditions have driven a price-competitive approach, even in high-end applications. The cost of use of the package must be lower even if advanced materials are used. A new, more cost effective, organic flip chip package substrate technology has been developed, prototyped, qualified, and is being ramped into production. This laminated substrate technology uses an engineered composite dielectric combined with advanced fabrication techniques to produce very high-density organic substrates.

The dielectric material boasts a Dk of 3.2 and a dissipation factor of 0.002 (at 9.3GHz). Standard design groundrules of the technology allow:

  • 20µm lines/30µm spaces
  • blind and buried vias with diameters of 40µm
  • dielectric thickness of 30µm
  • via densities > 2400/cm2
  • full array flip chip pitch of 180µm
  • package body sizes up to 55mm
  • ability to add embedded capacitance
  • The technology has been used to fabricate 45mm by 45mm test vehicles having die of 19mm by 19mm with more than 8000 total I/O. In this paper, we will discuss the construction materials, process technology, substrate reliability, assembly results, and package reliability using this new technology.

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