SMTA International Conference Proceedings


Author: Mradul Mehrotra et al.
Company: Raytheon Missile Systems
Date Published: 9/26/2004   Conference: SMTA International

Abstract: Raytheon Missile Systems (RMS) continues to use electronic packaging technologies such as Ball Grid Arrays (BGA), Chip Scale Packages (CSP), and Stacked Chip Scale Packages in its system designs. As the demand continues to drive towards higher density packaging along with a corresponding increase in functionality, component package sizes have also continued to increase.

In many cases, this increase in performance also results in increased component costs. As sizes continue to increase, the design and construction of the package itself can begin to have major impacts on the assembly/rework process. One of the major factors/variables that RMS has had to deal with is component warpage/displacement. This is due to increased functionality which drives the need for finer pitch and in some cases, increased package size, which increases the DNP (Distance from the Neutral Point).

Using analysis tools such as Shadow Moiré Interferometry may be necessary to understand the root cause of this problem and provide a direction to a possible solution. Tighter process controls, along with optimized temperature profiles may need to be established in an attempt to eliminate or at least reduce the effects of the warpage. This paper will discuss some of the key elements inherent to the aforementioned problem.

Key Words: BGA, ASIC, PWB, Warpage, Co-planarity, Shadow Moiré. X-Ray, Solder Reflow Profile and Rework

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