SUB 100 nm SILICON - THE IMPACT ON NEXT GENERATION IC PACKAGINGAuthor: Nick Pearne
Company: BPA Consulting Ltd.
Date Published: 9/26/2004 Conference: SMTA International
Although assembly and packaging costs are expected to decrease over time on a cost-per-pin basis, the package pin count is increasing more rapidly than cost-per-pin is decreasing. This explosion in pin count is increasing not only the absolute cost of packaging on a per-chip basis, but also the substrate and system-level packaging costs. The combination of mechanical, electrical and cost challenges for the package mean that concurrent chip and package design is becoming an essential element of successful product introduction. Today true co-design still remains an elusive goal for the EDA industry.
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