SMTA International Conference Proceedings


SUB 100 nm SILICON - THE IMPACT ON NEXT GENERATION IC PACKAGING

Author: Nick Pearne
Company: BPA Consulting Ltd.
Date Published: 9/26/2004   Conference: SMTA International


Abstract: Feature sizes have continued to reduce, offering the cost advantage as more and more functionality and thereby value is created on the silicon surface. While feature sizes reduced down to 180nm, the interconnect dielectric for the on chip interconnect has remained Silicon Oxide with excellent physical properties. With the step down below the 130nm node, local dielectric conditions can demand new low-k materials. So far these low-k materials have demonstrated mechanical properties offering less than 5% the performance of SiO2. Successful packaging must reduce the physical problems at the dielectric levels. At the same time the metrics of chip to next level packaging are set to reduce bring additional challenges to the packaging capability.

Although assembly and packaging costs are expected to decrease over time on a cost-per-pin basis, the package pin count is increasing more rapidly than cost-per-pin is decreasing. This explosion in pin count is increasing not only the absolute cost of packaging on a per-chip basis, but also the substrate and system-level packaging costs. The combination of mechanical, electrical and cost challenges for the package mean that concurrent chip and package design is becoming an essential element of successful product introduction. Today true co-design still remains an elusive goal for the EDA industry.



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