STUDY OF ENCAPSULATION PROCESS AND MATERIALS FOR MATRIX ARRAY OVER-MOLDED FLIP CHIP CSPAuthor: Kai-Chi Chen et al.
Company: Industrial Tech Research Inst
Date Published: 2/10/2004 Conference: Pan Pacific Symposium
A 3×3 chips area array flip chip test vehicle was designed for this study. The new technology shows many advantages such as: high electric performance, low cost, good reliability property, high throughput, thinner package, and void free during encapsulating process. Not only remarkable down-sizing, but also a new developed package shows good soldering resistance.
OFCSP is developed by both vacuum molding and vacuum printing processes and fine filler encasulant materials for simultaneous encapsulating process without void. The perfect void-free property of printing material could be achieved by vacuum printing machine and cured in the pressure oven. Thin over-coating layer was successfully filled by suitable molding material and transfer molding machine. It can pass level 3 and level 2 condition of JEDEC standard under 245oC or 265. reflowing test.
It can also pass the reliability testing items including PCT, TCT and HST after pre-condition of JEDEC level 3. Since the perfect molded property can be achieved by the combination of package structure, process and encapsulant properties, the package technology developed in this study can be applied for more advanced package such as paper-thin package, FC/WB embedded stacked package etc.
Key words: flip chip, transfer molding, over coating, matrix array, vacuum printing, pressure oven.
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