Pan Pacific Symposium Conference Proceedings


ASSEMBLY IMPROVEMENTS BY CONTROLLING PLACEMENT

Author: Terence Q. Collier
Company: CVInc.
Date Published: 2/10/2004   Conference: Pan Pacific Symposium


Abstract: Post reflow yield losses cost PCB assemblers tens of millions of dollars per year! Millimeter per millimeter, a populated post reflow finished PC board may represent the costliest square footage on earth. With bare boards costing upwards of thousands of dollars, a fully loaded PC board may have individual components equally as expensive. The manager(s) responsible for process yield have an urgent need to coordinate efforts to identify "marginal" processes, address root cause analysis and to implement process improvement initiatives to improve the bottom line.

During assembly, placement of the IC package can lead to defects and yield loss. IPC 7095 highlights criteria for solder bump failure as a result of poor assembly and fabrication. Unfortunately most manufactures of flip chip do not take head to IPC 7095 during the assembly operation.

The same spec used as an accept reject criteria for boards can also be used as a criteria for flip chip assembly. Here poor placement and alignment of electrical test probe needles cause the defects. The variation can come from a number of areas including the probe needle itself. The CSP assembly shop could suffer yield loss due to poor processes and not be aware that the root cause lies upstream.

Unfortunately those marginal processes prevent optimum efficiency and the implementation of tools to improve manufacturing techniques and likewise reduce process variation. A process must be brought into control to implement techniques such as JIT, lean manufacturing, Kaizen, etc. Last, the repair, downtime and yield loss associated with poor quality not only burdens costing structures, but also impairs the ability to accurately forecast production builds, staffing and raw material needs.

Table 1 Sample PCB Repair Costs at 2, 4 and 6 Sigma The raw materials populating boards is becoming an ever increasing mix of components that include small footprint devices with hidden solder joints (BGA, CSP, etc) and modular packages. Industry predictions for CSP-type packages are growth from 10% to over 60% in the next three to four years. These newer packages, more sensitive to placement errors (due to smaller geometry and hidden solder connections), require solutions that provide real-time process details as a mandate for improving PCB yield.

Looking further upstream in the manufacturing process, part of the process variation can be isolated to electrical test and probe. It is well established that the planarity of the BUMP "plane" can jeopardize yield and reliability. Poor probe processes introduce variation in the final assembly stages that might be incorrectly assigned to that process station.

This paper has been written to provide the audience with an overview of some root cause areas to investigate. Table 1 suggest possible dollar values that can be recovered as well as increased reliability suggest that upstream process control is critical to not only the CSP assembly in house, but the final product deliver to the customer as well.

Key words: standards, assembly, test, placement.



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