Pan Pacific Symposium Conference Proceedings


Author: Terence Q. Collier
Company: CVInc.
Date Published: 2/10/2004   Conference: Pan Pacific Symposium

Abstract: Testing CSP devices can be tricky. There are a number of new technologies in probe card design, as well as spins on older card technologies, that suggest improvements in yield and process cycle time. Does one technology truly represents a significant improvement over another technology? A typical, bare bones probe card can cost around $50,000. Most product lines might require 6-12 cards to support manufacturing and delivery schedules at a given instant in time.

The math quickly shows that for the life of a product line, probe cards cost represents a significant cost. Newer probe cards claim improvements in manufacturing, yield and cycle time. The premium for this suggested improvement in probe cards costs of $150k to $200k dollars for cards to support high pin count devices. The premium cost does not include special cleaning requirements, typically off-line, hardware and process controls required to support newer card designs.

The equipment never keeps up with the technology. While device and chip scale packaging has brought small to a new meaning, in many cases the ability to isolate and test devices is restricted. Downstream test equipment tolerances can exceed the tolerances on the device features. For example, at electrical probe, the equipment tolerance stack might add up to a dimension greater than the solder bump itself. Part of the error is attributed to the probe card but a great part can also come from other probe hardware variables.

Eliminating, rather reducing, one variable, the probe card, in some cases introduces new problems. The newer cards are typically more sensitive to system error and can tolerate much less setup error. The result of setup error can lead to probes missing the target (false fails and yield loss), striking a bump off center creating a shear moment (yield loss, reliability issues and qual failures), or even adding deep recesses in the bumps that might lead to voiding at the solder joint interface (voids greater than 25% to 50% in the solder ball).

While IPC 7095 provides a good "package" reference to the allowable void at the interface, it serves as a good flip chip qualification standard. In the determination if a "new" solution is needed to solve the problems at probe or assembly, one should first seek to determine the root cause before investing the money required to support such new infrastructure. A number of test sites have found that the cost of the new probe cards only add to the losses as the root cause of the problem was not necessarily the probe card.

This paper helps those that test, assemble and final test determine what is required to improve the process and recover the dollars lost to process misunderstanding and variability. This paper is also intended overview the difference between probing pads and bumps.

Key words: market trends, assembly, test, ROI.

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