Pan Pacific Symposium Conference Proceedings


Authors: Dr. Bruce King and Dr. Marcelino Essien
Company: Optomec, Inc.
Date Published: 2/10/2004   Conference: Pan Pacific Symposium

Abstract: Currently, only a small percentage of IC die have been designed to be easily assembled into today’s large number of package styles. Many chip scale packages require redistribution of the chip interconnects to support increased I/O counts. This is particularly evident in wafer level packaging (WLP). The problems are many. First, semiconductor design infrastructure has not kept pace with assembly technology developments - package styles are leading the design effort. And second, the need to be first to market forces many package manufacturers to use available die designs to meet their customer’s requirements. This leaves two options - redesign the chip to fit the package style, or redistribute the bonding pads to fit the application.

Even if the design infrastructure were in place, redesign is out of the question. First, the cost associated with taking a designed and tested chip back to the drawing board is prohibitive. Second, there’s the time involved with redesign of an IC. Third, the number of different package styles would require an IC to go through several iterations of design, one for each differing style of package, each with a differing range of interconnects. Fourth, the creation of a new set of mask masters is cost-prohibitive. And finally, by the time the new design is ready for production, the package style probably would have changed - again.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819