CORRELATION OF SOLDER JOINT RELIABILITY OF µPGA SOCKET TO PACKAGE FLATNESS AND PCB WARPAGE *PHASE I - PCB WARPAGE UNDER THERMAL REFLOW BY MOIRE...Author: Dr. Paul P.E. Wang et al.
Company: Sun Microsystems, Inc.
Date Published: 2/10/2004 Conference: Pan Pacific Symposium
Shadow Moiré Interferometry was conducted on the test vehicle, with paticular attention on the µPGA socket site, as well as on the top of µPGA socket, to assess the PCB warpage and package flatness under the emulated reflow process. Then an FEM model was created with variations of stack-up, layer count and copper foil thickness, to simulate the PCB warpage under similar reflow cycles.
Finally, the trend of the data from Moire emulation and FEM simulation were benchmarked. The relationship of mechanical strengthening mechanism of eutectic quasi-laminate or rod-like a and ß phases formation and stretched crack path were correlated to the FEM simulated cooling rate and peak reflow temperature In Phase II, the correlation of solder joint reliability of µPGA socket to PCB warpage and socket flatness as a future study is reported.
In Phase III, the methodology to established the residual stress under mechanical bending to the reliability scale is proposed. Field mechanical stress will be monitored and FEM modeling will be conducted to assess and infer beyond the limitation of instrumentation.
Key words: µPGA, micro pin grid array, DOE, design of experiment, reliability, shadow moiré, shadow moiré interferometry, DC, daisy chain, 5DX laminography, SVS, IST, process optimization, ATC, pre-mechanical stress emulation, stain, strain rate.
* See also the article "Phase II - PCB Warpage Under Thermal Reflow by Moire Emulation and FEM Simulation".
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