Pan Pacific Symposium Conference Proceedings


WAFER LEVEL CHIP SCALE PACKAGING BENEFITS FOR INTEGRATED PASSIVE DEVICES

Author: James L. Young
Company: Intarsia Corporation
Date Published: 2/2/1999   Conference: Pan Pacific Symposium


Abstract: Chip scale packaging continues to draw a lot of attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (BGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages which offer the fastest path to small form factor, high performance, cost effective solutions.

Current portable/mobile consumer devices continue to place demands on designers for miniaturized solutions whose cost must be lower than previous products. Miniaturization and lower cost cannot be exclusive events and in fact the two must go hand in hand. RF and wireless systems in these handheld devices add a dimension of complexity that requires unique solutions. More functions continue to be added to handheld products and yet the overall size of the products continues to shrink. Chip scale packages have offered a promising solution to some integrated circuits but to date no solution has been offered for passive devices whose numbers continue to grow. In cell phones, passive to IC ratios are in the range of 12 to 1. In a typical cell phone, passive counts range from 200 to 400 and occupy a large percentage of the circuit board space. Passives can represent 80% of the size and 95% of the components. [1] As frequencies go higher, the discrete thick film passive devices cannot provide the RF performance necessary to meet design requirements.

There is a growing amount of interest in integrated passive devices (IPDs) and the role they can play in providing high performance solutions, such as RF subsystems, reducing board level complexity, and improving ease of passive assembly. The one issue that has held integrated passives back has been conventional packaging. The cost of integrated passives in conventional packaging has been too high for widespread adoption of IPDs. Wafer level chip scale packaging, combined with a thin film passive device technology and a large area format manufacturing capability offers a cost effective solution, as well as providing a form factor compatible with existing surface mount assembly operation. Key words: Wafer level packaging, chip scale packaging, integrated passive devices



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