To stay abreast of the fast changing electronic packaging technology, Raytheon Systems Company (RSC) has been actively involved in many consortia activities with a view of leveraging from the commercial industry. Since the beginning of 1997, Raytheon and many diverse companies teamed up to form the “CSP consortium”, with Jet Propulsion Laboratory (JPL) as coordinator. The objective of the consortium is to assess design, microvia printed wiring board (PWB) fabrication, PWB assembly, and reliability of emerging high density, area array packaging technologies such as Chip Scale Packaging (CSP). Chip Scale Packaging technology along with Ball Grid Array (BGA) have changed the landscape of the electronic packaging industry. Many commercial, aerospace, and defense companies are quickly realizing the benefits of using these technologies. As packaging densities continue to increase, the design criteria become increasingly critical. Since there are so many CSP configurations currently on the market, it is necessary to develop standard guidelines in the design, fabrication of the PWB, and the required assembly process using CSPs. As part of the consortium agreement, Raytheon is responsible for the design and the fabrication of the microvia PWB test vehicles. The focus of this paper is to highlight the attributes of the consortium, lessons learned, and issues associated with CSP board design, microvia PWB fabrication, and assembly in non-commercial applications.
Keywords: CSP, BGA, Consortium, In-kind, PWB, Microvia, HDI, Test Vehicle, Polyimide