Pan Pacific Symposium Conference Proceedings


Author: David Scheid
Company: Silicon Graphics
Date Published: 2/2/1999   Conference: Pan Pacific Symposium

Abstract: A thin film interconnected, 3D package with area array I/O has been implemented using conventional CMOS ICs and SRAMs. The completed MCM has 4 ASICs, 36 LICA capacitors and 8 memory cubes with each cube consisting of eight 4 Mb SRAM die. The memory cube measures 15 mm by 7 mm by 3.8 mm. The individual memory die after dicing are mounted and coated with a PECVD SiO2 film followed by a blanket sputter deposition of Ti/Cu/Pt on the top and the diced edge. Patterning is done using a Kr/F excimer laser to define the routing of the perimeter pads on top of the SRAM over the edge of the die. Bonding of the die into a stack is done using a thermoplastic polymer. Memory cube processing allows each of the 352 die pads to be individually addressable. All components are flip chip attached to a Cu-PI thin film interconnect structure which was sequentially processed on a ceramic substrate. The MCM is attached to a PCB by means of a column grid array. The thin film MCM with the attached capacitors provides a routing capacity of 400cm/cm2 and a controlled impedance environment for signal transmission and power distribution. This paper details the design, fabrication and initial reliability results of this package. Key words: MCM-D, Cu-PI, Interconnect, 3D Memory, and Laser Patterning

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