Pan Pacific Symposium Conference Proceedings


Author: Rao R. Tummala
Company: Georgia Institute of Tech.
Date Published: 2/18/2003   Conference: Pan Pacific Symposium

Abstract: As microsystems continue to move towards higher speed and microminiaturization, the demands for interconnection density, both on the IC and the package, increase tremendously. With the shift towards nano ICs by 2003 at or below 100 nm features, pitch of area array I/Os of the nano ICs needs to move towards 100 to 20 microns [1]. What would be the packaging technologies that will make this happen? Would they be at wafer level? Would this be micro- SMT?

Increasing system functionality with system-on-a-chip or system-in-package will place demands further to support extremely high digital and RF speeds beyond 10 GHz, and optical data rates beyond 100 Gbps. A completely new paradigm shift in high density packaging is required to meet these complex requirements. Current trends, both in IC and systems packaging including SIP and wafer level packaging are steps in the right direction, but they are at IC packaging level only.

What will be th next level of intercoonnections that are typically done by SMT technologies today. Is it possible that these level of interconnections would merge with the IC level interconnections so as to end up with one set of interconnections? The Packaging Research Center at Georgia Tech has been developing system-on-a-package (SOP) technology to integrate digital, RF, and optical, all on a multi-function, microminiaturized board.

Such a board is connected with micro- SMT in the short term and nano- interconnections in the long term. This paper reviews systems, IC, and high density packaging trends and summarizes some of the latest micro and nano- SMT interconnection technologies that are on the horizon.

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