Pan Pacific Symposium Conference Proceedings


DESIGN ISSUES RELATED TO AREA ARRAY PACKAGING TECHNOLOGY

Authors: Steve R. Stegura and Emmanuel J. Siméus
Company: Raytheon Missile Systems
Date Published: 2/18/2003   Conference: Pan Pacific Symposium


Abstract: Design errors continue to be one of the hidden costs in manufacturing Surface Mount Technology (SMT) and Circuit Card Assemblies (CCA) products. A minimal error is far too many as relates to high performance and avionics applications, which can cost many thousands of dollars.

Therefore, it is critical for the Computer Aided Design (CAD) designer, Printed Wiring Board (PWB) fabricator and the SMT process engineer to work together as an integrated team to insure design errors are caught in the early stage of the design before PWB fabrication in order to mitigate the risk of high costs and schedule.

This paper will present the decimal-to-metric conversion error and vice versa, often made by the component engineer or CAD designer and a certain percentage of "off-set" introduced in some specific Ball Grid Array (BGA) and Chip Scale Packaging (CSP) designs in order to study the effect on assembly and second level reliability.

Key words: design, BGA, CSP, high density, offset, run-out, PWB, CAD, test vehicle.



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