Pan Pacific Symposium Conference Proceedings


Authors: Thomas Goodman and Peter Elenius
Company: E&G Technology Partners, LLC
Date Published: 2/18/2003   Conference: Pan Pacific Symposium

Abstract: Wafer Level Packaging (WLP) has enabled new advances in the miniaturization and cost reduction of portable products through its chip-size form factor and parallel (wafer-level) processing. Devices such as EEPROMs, integrated passive devices (IPDs) and analog chips that are packaged in WLP are now used extensively in mobile phones and other portable consumer products. In addition, WLP is being adapted for new devices such as power MOSFETs to enable their use in miniaturized equipment. Clearly WLP represents one of the most exciting and innovative frontiers in our industry today.

The use and development of WLP is being both driven and limited by the demanding requirements of a variety of high volume devices. Reliability, testability, and cost are among the hurdles to be cleared prior to application to a device. In addition, a number of other technologies successfully compete for sockets in the same products.

Yet WLP is being designed into an increasing number of applications, spurring the industry to continually develop and advance the technology. This paper will present an analysis of the technologies and market trends that have not only brought WLP to its present state but still drive it today, and provide clear insight to its future path.

Key words: wafer level package, portable products, chip size package, form factor.

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