NEPCON West - Fiberoptic Expo Conference Proceedings


ADVANCED CHIP TEST TECHNIQUES AT HIGHER INTEGRATION LEVELS

Author: Ron Press
Company: Mentor Graphics Corp.
Date Published: 12/3/2002   Conference: NEPCON West - Fiberoptic Expo


Abstract: Testing assemblies with ICs can be supercharged by re-using test features in the ICs. Many advanced test features are designed into ICs to enable very thorough IC testing. If properly designed with a simple interface, IC tests can be re-used during the test of the ICs in higher levels of integration. Test requirements for Integrated Circuits have been steadily increasing with ever-growing gate count per IC and the need for more thorough testing.

Design-for-Test (DFT) techniques and tools have significantly improved over the years to keep up with these requirements. A common IC test practice is to control and interface to the IC test features through the IEEE 1149.1 boundary scan port.The boundary scan port provides the key to a simple test interface to perform thorough IC tests at higher levels of assemblies.

As a result, testing of hybrids, boards, MCMs, and other assemblies can be improved by re-using IC tests. IC test features that can be re-used at higher integration levels include internal logic testing through scan or logic BIST, memory testing with memory BIST or macro testing, and more. Even more advanced at-speed testing practices can be applied to ICs for testing timing problems or verifying critical paths with the use of a moderate speed interface to the boundary scan port.

Key words: boundary scan, BIST, pattern compression, scan, at-speed test, SoC.



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