ADVANCED CHIP TEST TECHNIQUES AT HIGHER INTEGRATION LEVELSAuthor: Ron Press
Company: Mentor Graphics Corp.
Date Published: 12/3/2002 Conference: NEPCON West - Fiberoptic Expo
Design-for-Test (DFT) techniques and tools have significantly improved over the years to keep up with these requirements. A common IC test practice is to control and interface to the IC test features through the IEEE 1149.1 boundary scan port.The boundary scan port provides the key to a simple test interface to perform thorough IC tests at higher levels of assemblies.
As a result, testing of hybrids, boards, MCMs, and other assemblies can be improved by re-using IC tests. IC test features that can be re-used at higher integration levels include internal logic testing through scan or logic BIST, memory testing with memory BIST or macro testing, and more. Even more advanced at-speed testing practices can be applied to ICs for testing timing problems or verifying critical paths with the use of a moderate speed interface to the boundary scan port.
Key words: boundary scan, BIST, pattern compression, scan, at-speed test, SoC.
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