DEVELOPMENT OF THE REAL CHIP SIZE PACKAGE USING THE WAFER LEVEL ASSEMBLY PROCESSAuthor: Ichiro Mihara
Company: CASIO COMPUTER
Date Published: 2/2/1999 Conference: Pan Pacific Symposium
The wafer with Cu bump is encapsulated using transfer molding method or printing method. Then the encapsulated wafer is singulated into individual LSI chip.
To establish this assembly process and the high quality package, several technologies seemed to be difficult. 1.To perform an uniform height and shape of Cu bump by grinding for solder joints reliability, 2.To perform a relation of internal connection between Cu patterns and Al pad nearby for thermal shock reliability, 3.To optimize an encapsulant material and method for solder reflow resistance and solder joint reliability. This paper will describe the assembly process and reliability of this package.
INTRODUCTION For the trend of high-density LSI packaging showing the relation between terminal-pitch and packaging-density.
Peripheral terminal packages have DIP, SOJ, SOP, QFP, TCP, and bare chip, and area terminal packages have BGA, FBGA, and bare chip.
Area terminal packages can have more terminals than peripheral terminal packages at the same terminal pitch. In other words, the area terminal packages can have higher mounting densities.
Recently, there are strong demands for relatively small size packages, especially in a portable communication device markets. To minimize the mounting area on a PCB, bare chip using flip chip technologies are growing gradually, but there is the solder joints reliability to not performed.
Today, we'd like to present a new style of package. This is a wafer-level assembly CSP. It is expected to minimize the mounting area like bare chips and assure high reliability like the FBGA packages. The wafer-level assembly CSP will be suited for mobile phones, wrist products, camcorders, and amusement products.
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