NEPCON West - Fiberoptic Expo Conference Proceedings


BACKPLANE ASSEMBLIES FOR > 10 Gb/s

Authors: Franz Gisin and Dr. Sundar Kamath
Company: Sanmina-SCI
Date Published: 12/3/2002   Conference: NEPCON West - Fiberoptic Expo


Abstract: Physical interconnects, including backplane assemblies, distort the wave-shape of high speed digital data packets as they pass through the interconnect. The distortions introduce transmission errors that degrade the performance of interconnects operating at speeds of 10 Gb/s and beyond. Traditionally, a number of system level techniques have been used to minimize the impact of these distortions including redundancy; error detection/correction and transfer function compensation. However, all these solutions add to the total interconnect cost because they do not directly address the underlying reasons why the interconnect introduces distortions in the first place.

But now a number of technological advances in the design and manufacture of backplane assemblies significantly decrease distortions, thereby increasing the quality of the interconnect while reducing the need for complex and expensive system level error detection, correction and compensation schemes. This paper presents some some examples of how a properly designed and manufactured backplane assembly improves the overall bit error rate of high speed printed circuit board interconnects.

Key words: backplane, bit error rate, crosstalk, high speed interconnects, jitter, signal distortions, vias.



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