Pan Pacific Symposium Conference Proceedings


VIA-FILLING USING ELECTROPLATING FOR BUILD-UP PRINTED CIRCUIT BOARDS

Author: I. Kobayashi
Company: Kanto Gakuin U.
Date Published: 2/2/1999   Conference: Pan Pacific Symposium


Abstract: Recently, the demand for miniaturization of printed circuit boards has been increasing, because the electronic devices have been sharply downsized. Therefore, high activity is engaged into the development of build-up printed circuit boards as the alternative technology to the conventional rnulti-layer printed circuit boards with through-holes. In this new technology, the plating of micro-vias is applied to the connection between each conductive layers. However, the planerization of dielectric layer on the micro-vias is very difficult in the case of the conventional plating process or conductive paste method.

In previous reports, we examined the filling of micro-vias by the electroless copper plating and electroplating with the applied periodic reverse current, In this report, we investigated the filling of micro-vias by the electroplating with direct current and pulsed current, with a variety of additives and controlled current wave forms.As a result, the selection of proper additives was effective to fill rnicro-vias with copper even under the condition of electroplating applied direct current. In the case of electroplating applied pulsed current, the filling of micro- vias could be achieved more easily. Moreover, the concentration of copper sulfate in the electroplating bath was highly correlated to the filling property and higher copper concentration showed the good performance for via- filling. Key words : Build-up Process , Via-hole , Filling ,Electroplating



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