SMTA International Conference Proceedings


Author: Michael Spofford
Company: Lattice Semiconductor, Inc.
Date Published: 9/22/2002   Conference: SMTA International

Abstract: In today’s world of circuit board design the need to develop boards and systems which support boundary scan testing is often times imperative. Designers are being asked to increase functionality while decreasing the size and cost of their designs.

Lattice Semiconductor recognized the growing demand for boundary scan testability and created reference designs to address the needs of both design and test engineers. These reference designs create multiple "secondary" boundary scan chains which are controlled from a single "primary" boundary scan chain simply by serially inputting command information via the TDI signal.

The designs can 1) be used to test a single board or 2) be used to test multiple boards within a system using a "multidrop addressing" technique. By creating multiple secondary chains, designers have the ability to place PLD’s, processors, memory and daughter cards on separate unique chains.

By placing a reference design in a non-volatile CPLD, designers have the ability to add their own application specific design while making use of the CPLD’s features to customize their solution. The advantages of using a programmable logic device to control both board and system level boundary scan testing capability will be discussed.

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