SMTA International Conference Proceedings


Authors: Reza Ghaffarian, Ph.D.
Company: Jet Propulsion Laboratory
Date Published: 9/22/2002   Conference: SMTA International

Abstract: System in a package (SIP) development is a response to an increasing demand for integration of different functions into one unit to reduce size and cost and improve functionality. Qualification of newly developed multifunctional electronics are becoming complex at the package level and even more at the second and system levels. For one die package, after many years of data collection, just recently industry agreed to release an industry-wide specification.

Probability risk assessment (PRA), implemented by NASA for spaceflight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further to electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries).

It will report on a few other unique qualification approaches that are currently being implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). Cycles-to-failures (CTFs) test results for temperature ranges of -30 to 100°C and 0 to 100°C (two profiles) are compared.

Finally, it will review finite element analyses performed for optimization of a unique silicon base SIP package assembly with five chips on a microboard. Qualification approach for level 1 and level 2 of this SIP will also be presented.

Key words: probability risk assessment, Weibull, LogNormal, ball grid array, BGA, FCBGA, IPC9701, solder joint reliability, systems-in-a-package, SIP.

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