SMTA International Conference Proceedings


CSP AND BGA ASSEMBLY RELIABILITY IN A FAST RAMP RATE THERMAL CYCLE ENVIRONMENT

Authors: Reza Ghaffarian, Ph.D.
Company: Jet Propulsion Laboratory
Date Published: 9/22/2002   Conference: SMTA International


Abstract: A JPL-led chip scale package (CSP) consortium composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources in order to develop quality assurance techniques and evaluate the reliability of mixed area array technologies, chip scale packages (CSPs) and ball grid arrays (BGA), for a variety of projects.

The Consortium selected fifteen different packages with I/Os ranging from 48 to 784 and pitches varying from 0.5 to 1.27mm. The packages were mounted on multilayer FR-4 printed wiring boards (PWBs). These test vehicles (TV-2) were subjected to numerous thermal cycling conditions including - 55°C to 125°C with a near thermal shock condition.

Cyclesto-failure (CTF) test results up to 1,500 cycles are compared under this condition for 784 I/O FCBGA (fine pitch BGA), 175 I/O FPBGA (flip chip BGA), and 313 I/O PBGA (plastic BGA). Inspection results along with SEM (scanning electron microscopy) and optical cross-sectional photos revealing damage and failure mechanisms are also included.

Key words: CSP, BGA, FCBGA, FPBGA, reliability, solder joints.



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