Journal of SMT Article
RELIABILITY ASSESSMENT OF FLIP CHIP ON LAMINATE CSP
Company: Analog Devices
Date Published: 7/1/2002 Volume: 15-3
Despite the long-time existence of flip chip, for each specific product and package application it remains a challenging task to select the right materials and right technology for optimized performance and reliability at comparatively low cost. In fact, alternative materials and process technologies for flip chip remain open areas of investigation to meet newer product challenges, which in turn motivates studies on new failure mechanisms and design optimization.
There is also a need for industry standards for testing and characterizing packages with flip chip technology. This paper presents a case study of reliability assessment of a low cost flip chip on laminate CSP for embedded DSP application. A daisy-chained test die was packaged in both molded and exposed die forms. Parametric studies included die thickness and passivation materials. Failure mechanisms, design and assembly factors are discussed.
Key words: Flip chip, laminate, CSP, reliability, failure analysis, failure mechanism, warpage measurement, die thinning, underfill, polyimide.
Members download articles for free:
Not a member yet?
What else do you get when you join SMTA? Read about all of the benefits that go along with membership.
Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.