Journal of SMT Article


Author: Reza Ghaffarian
Company: Jet Propulsion Laboratory
Date Published: 1/1/2002   Volume: 15-1

Abstract: A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. Previous test results have now been published as a chip scale package guidelines document and distributed by Interconnection Technology Research Institute (ITRI).

The Consortium assembled fifteen different packages from 48 to 784 I/Os and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring boards (PWBs). In addition, two other test vehicles built by two team members, each had a control wafer level CSP package for data comparison. To meet various qualification needs of team members, assemblies were subjected to thermal cycling ranges representative of military, space, and commercial. The most rapid qualification was performed using thermal cycling in the range of –55 to 125°C with a near thermal shock ramp rates. Cycles-to-failure (CTF) test results to 3,000 cycles performed under this and three other thermal cycling ranges including 0 to 100° C are presented. The effect of ramp rate increase on CTFs and failure mechanisms for thermal cycling performed under near thermal shock and thermal cycle in the range of –55 to 125°C are also presented.

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