Journal of SMT Article

3D Wafer Level Packaging by Using Cu-Through Silicon Vias for Thin MEMS Accelerometer Packages

Authors: L. Hofmann, I. Schubert, D. Wünsch, R. Ecke, K. Vogel, K. Gottfried, D. Reuter, M. Rennau, S.E. Schulz, T. Geßner
Company: Fraunhofer Institute for Electronic Nano Systems and Technische Universität Chemnitz
Date Published: 3/1/2017   Volume: 30-1

Abstract: Technologies for 3D-Wafer Level Packing (WLP) of Micro electro Mechanical Systems (MEMS) are described with respect to devices that find applications in thin packages (e.g. smart cards). An aspired final device thickness in the range of 350…400 µm is achieved by using Cu based Through Silicon Vias (TSV’s) Wafer Level Bonding (WLB) wafer thinning. In particular, two Via Last approaches using TSV’s in the cap wafer and device wafer, respectively, are described.

According to this, two WLB technologies are investigated: glass frit bonding as well as Silicon Direct Bonding (SDB) of Si-SiO2. The first technique has been demonstrated using a MEMS accelerometer including electrical tests and cross sectional analysis.

Keywords: 

3D-WLP, MEMS, Through Silicon Via, Silicon Direct Bonding, Thin Package



Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is prohibited. Downloaded papers must only be stored on a local hard drive and not in a shared repository either internal or external.


Back


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344

Phone 952.920.7682
Fax 952.926.1819
Home
Site Map
Update Your Info
Related Links
Send Us Feedback
Contact Us
Privacy Policy
↑ Top