Multi-Variable Multi-Objective Design Optimization of BEoL/ fBEoL Structure in a Flip Chip Package during Chip Attachment to Substrate
Authors: Fahad Mirza, Hardik Parekh, Tejas Shetty, and Dereje Agonafer Company: University of Texas at Arlington and PV Fluid Products Inc. Date Published: 10/1/2014
Abstract: Semiconductor industry has recognized the need to replace traditional Al/SiO2 interconnects with Cu/low-k interconnects in the mainstream electronic devices following the latter’s significant impact on the RC delay and cross-talk between metal lines. The low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. However, low-k dielectrics have lower modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poor adhesion as compared to SiO2. Thus, low-k dielectric integration in the contemporary IC packages poses a significant reliability challenge. Delamination along the metal-dielectric interfaces and crack propagation in the dielectric layers has been widely observed during cooling from higher temperatures and thermal excursions. Flip-chip attachment process for Pb-free assemblies (cooling from ~200°C to room) can result in critical damage in the nano-scale Cu/low-k interconnect region and/or the flip chip bumps (C4). The objective of this study is to assess and improve the reliability of Back-end-of-line (BEoL) region comprising of the Cu/low-k interconnect layers and the Far-BEoL (fBEoL) region consisting of the C4 µ-bumps during the process of die attachment to substrate. The analysis has been done for a specific die to substrate size ratio by varying the design parameters including substrate thickness and µ-bump dimensions (diameter and stand-off height). Preliminary parametric study has shown that the variation in the concerned design variables has a significant effect on the f-BEoL and BEoL layer damage . However, there is a trade-off between the µ-bumps and the dielectric damage with the bump size, thereby raising a need to perform a multi-design multi-objective design optimization to have an optimized design. Multi-objective design optimization has been carried out to improve BEoL/fBEoL reliability under reflow loading by minimizing the following objective functions 1) maximum strain energy in µ-bump and 2) peeling stress in dielectric region (low-k layers). This work is of immense importance from process integration standpoint. It can provide a quantitative upstream guideline to the process/electrical team on the BEoL/fBEoL design parameters for co-optimization.