Journal of SMT Article

3-D Fracture Analysis of the BEoL Region of a Flip Chip Package During Die Attach Process

Authors: Zaeem Baig, Fahad Mirza, Hardik Parekh, Dereje Agonafer
Company: University of Texas at Arlington
Date Published: 4/1/2014   Volume: 27-2

Abstract: As scaling of components continues, using SiO2 as a dielectric in the Back-End-Of-Line (BEoL) is no longer a viable option and can be replaced with low-k and ultralow-k (ULK) dielectric materials for advanced integrated circuits (IC) packaging solutions. The low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. However, low-k dielectrics have lower modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE), and poor adhesion as compared to SiO2. Thus, low-k dielectric integration in the contemporary IC packages poses a significant reliability challenge. Delamination along the metal-dielectric interfaces and crack propagation in the dielectric layers has been widely observed during cooling from higher temperatures and thermal excursions. This provides the impetus for this work. In this study, 3D finite element (FE) analysis is performed to demonstrate the thermo-mechanical response of the BEoL region of a flip chip package with Pb-free solder interconnects. Crack propagation in the low-k layers is analyzed under the loading when the die is attached to the substrate (reflow). J-integral obtained from the FE analysis is utilized to identify the dielectric layer most susceptible to crack propagation. Thickness of the metal layer, adjacent to the critical dielectric layer is increased and the new J-integral values are computed. This paper suggests reinforcing the critical low-k layer by increasing the thickness of the adjacent metal layer can be an effective way to mitigate the dielectric crack issue.


Low-K, Crack, Flip-Chip, BEoL

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