Journal of SMT Article


Author: Peter Elenius
Company: Flip Chip Technologies
Date Published: 4/1/1999   Volume: 12-2

Abstract: There has been a significant amount of work over the past five years concerning chip scale packaging. The majority of this work has been an extension of conventional IC packaging technology utilizing wire bonders and/or tab-type packaging technology. Handling discrete devices during the IC packaging for these types of CSPs has resulted in relatively high cost for these packages and lower IC package yields than desired.

This paper will present a new wafer-scale packaging technology called the Ultra* CSP. Advantages of this wafer-scale packaging concept includes commonality with standard IC processing technology for the majority of the packaging process.

This paper covers in detail the reliability results achieved for the Ultra CSP for a variety of package sizes and I/0 counts covering the range typically seen in microcontrollers, flash and new DRAM architectures. There will be significant discussion, as well, on optimization work done on board pad size, solder paste volume and solder paste type.

Key words: CSP, chip scale package, wafer-level packaging, Ultra CSP, IC packaging.

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819