Journal of SMT Article


Authors: Mudasir Ahmad and David Popovich
Company: Cisco Systems, Inc.
Date Published: 7/31/2009   Volume: 22-3

Abstract: With miniaturization and increasing wattage of devices, the total heat flux from electronic products is steadily increasing. Air cooling is still the primary means of heat transfer, and an ever increasing amount of heat is getting transferred into the Printed Circuit Board (PCB).

Increased wattage also means more power is carried by the PCB. As a result, the PCB is now becoming a critical source of heat. Localized heat generation means less heat is transferred from the devices through the PCB. In complex back-planes, mid-planes and line-cards, the PCB power architecture is quite extensive. As a result, it is becoming more critical to add more intelligence in the layout and design of the power architecture. An overly conservative power delivery architecture results in boards with higher layer count, which are expensive and less reliable.

Conventionally the geometry of the power architecture (traces and vias) in circuit boards is determined based on the temperature rise/unit length in a simple conductor mounted on a PCB coupon. This predicted temperature rise has been outlined in the IPC-D-275 charts.

It has already been shown that the temperature rise predicted by the IPC-D-275 charts is significantly different from the actual measured values [1]. Recently, efforts have been made to revise these charts. While simple configurations have been analyzed, an experimentally validated, non-proprietary approach has not been developed to study the temperature rise of traces/vias in multilayer structures.

In this study, a novel approach has been developed to determine the temperature rise across traces and vias in multilayer structures. Coupled thermal-electric finite element models were developed to determine the voltage drop, current density and resulting temperature rise across each layer in the structure. The methodology is designed to accommodate large aspect ratios in the dimensions of a small trace and a large multilayer structure. The predicted external and internal trace temperatures have been validated with experimental measurements.

This numerical approach was also used to study via structures designed to improve wave solderability of through-hole structures. Parametric analysis was performed to determine the optimum number of peripheral vias and non-functional planes required for minimum temperature rise at a given current value.

Keywords: Coupled Thermal Electric, Finite Element Analysis, Joule Heating, Reliability, IPC-D-275, IPC 2221

Members download articles for free:

Not a member yet?

What else do you get when you join SMTA? Read about all of the benefits that go along with membership.

Notice: Sharing of articles is restricted to just your immediate work group. Downloaded papers should not be stored on an external network or shared on the internet.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344 USA

Phone +1 952.920.7682
Fax +1 952.926.1819