Journal of SMT Article


Authors: Satyanarayan Iyer and Krishnaswami Srihari
Company: SMART Modular Technologies, Inc. and State Univers
Date Published: 7/31/2009   Volume: 22-3

Abstract: The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to costeffectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The complex nature of stacked Chip Scale Package (CSP) components presents unique assembly challenges that needed to be studied and addressed. The purpose of this paper is to understand these challenges and present a recipe for reliably reflowing package stacked CSP components. The paper presents assembly process research for a new and complex package type.

The first segment of the research focused on evaluating the impact of the reflow profile peak temperature on Single Bit Errors (SBE). The second segment focused on reliability evaluation from a solder joint reliability perspective. The final recommendations were made based on the results of both segments of the research. Based on the test conditions used during this research, there was no difference in the results obtained for the three different peak reflow temperatures that were considered (230ºC, 237ºC and 244ºC) from the component degradation standpoint. Component degradation was measured in terms of SBEs. The reflow profile with a peak temperature of 237ºC, which is commonly used for leadfree soldering, yielded reliable results for assembling stacked CSP components, both from a component degradation and solder joint reliability perspective. Based on the findings, the lead-free stacked CSP components evaluated as a part of this research can be reliably assembled using the process recipe recommended in this paper.

Keywords: Stacked CSP, lead-free, reflow, SBE, solder, reliability.

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