Keynote Speaker

Dealing with the Challenges in the New Advanced Packaging Era

E. Jan Vardaman, TechSearch International, Inc.

Wednesday, June 5, 2019 | 1:00pm-1:45pm

E. Jan Vardaman

The role of packaging and assembly in the electronics industry is changing. In the high performance space, new packaging solutions are being adopted to achieve the economic advantages that were previously met with silicon scaling. Many of these options include heterogeneous integration in the form of silicon interposers, fan-out on substrate, and system-in-package. In the mobile space the introduction of 5G requires the development of new packaging solutions. Product ramps are steep and cost and performance targets must be met. The automotive sector with increased electronic content provides an attractive market, but reliability requirements are tough to meet. Challenges for packaging and assembly in this new era include chip package interaction (CPI) for devices fabricated with low-k and ultra-low-k (ULK) dielectrics. This presentation discusses the packaging changes and some of the issues being faced.

About the Presenter

Jan Vardaman is the editor of Surface Mount Technology: Recent Japanese Developments, co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbun), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the US mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, SMTA, and SEMI. She was elected to two terms on the IEEE CPMT Board of Governors. She received her BA in Economics and Business from Mercer University in Macon, Georgia in 1979 and her MA in Economics from the University of Texas at Austin in 1981.

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