The South East Asia Technical Conference on Electronics Assembly is a highly technical event that is focused on today's most important and timely issues. The drive for smaller, more functional consumer electronics along with the need for highly reliable electronics applications have kept the material, process and quality engineers busy planning for the future. These drive the many challenges that our industry faces today. We encourage our colleagues in Malaysia to come together to share their knowledge and their vision for addressing these challenges.
The conference is "claimable from HRDF under SBL scheme."
View the Technical Program Here!
Recent Advances in Flip Chip, WLCSP, and FOWLP
Wednesday, August 15th
John H. Lau, Ph.D., ASM Pacific Technology
Recent advances in (1) flip chip such as wafer bumping, package substrate, assembly, and underfill, (2) fan-in WLCSP (wafer-level chip scale package) such as relaxation layer and under-bump metallurgy (UBM)-free WLCSP, and (3) FOWLP (fan-out wafer-level packaging) such as chip-first with die face-down, chip-first with die face-up, and chip-last or redistribution layer (RDL)-first will be presented in this study. Emphasis is placed on the latest developments of these technologies in the past few years. Their future trends will also be discussed.
Professional Development Courses
Flip Chip, WLCSP, and FOWLP Assembly and Reliability
Tuesday, August 14
John Lau, Ph.D. Sr. Technical Advisor, ASM
The major trend in the electronic industry today is to make products such as smartphones, tablets, wearables, internet of things, etc. more personal by making them smarter, lighter, smaller, thinner, shorter, and faster, while at the same time making them more friendly, functional, powerful, reliable, robust, innovative, creative, and less expensive. As the trend towards miniature and compact products continues, the introduction of cool products that are more user-friendly and contain a wider variety of functions will provide growth in the market. Some of the key technologies that are helping to make these cool product design goals possible are flip chip, WLCSP (wafer-level chip scale package), and FOWLP (fan-out wafer-level packaging). Their PCB (printed circuit board) assembly and solder joint reliability will be presented and discussed in this lecture.
Understanding Parameters Affecting Barrel Fill in Wave Soldering Process
Wednesday, August 15
AF Ng, Consultant, Techment Consultancy Sdn Bhd
Conventional Wave Soldering has been employed for soldering of boards since long time ago. The related manufacturing personnel are well aware of common encumbering defects happen erratically with this process. Some of these defects encountered daily are bridging, solder skips, solder voids and insufficient barrel fill or hole-fill. Many of us would agree that we are still facing challenges on one of the common defects – poor barrel fill. The problem is confounded with currently High density/Multilayer thick PCB and applying Lead-free soldering. It is important for the Engineering personnel to understand the root causes of the defect, as it can be contributed by factors from board design, material procurement to equipment setting and maintenance. With these numerous factors implicating, the engineers involved must be equipped with sufficient knowledge on soldering fundamentals, laminate composition, thermal demands, design geometry, wetting mechanism during wave contact and equipment maintenance. Commonly, many engineers just adopt recommendations based on DOE results and hoping to get consistent good barrel fill, but mostly to their disappointment due to erratic parameter shift. Many engineers approach the problem by tweaking process parameters on fluxing, preheating, solder pot temperature, wave height adjustment and others, it merely be just a containment and not able to achieve consistent good barrel fill. We need a practical approach in tackling this vexing problem. To do that, one needs to know the fundamentals of wettability involving molten solder. The molten solder wicks up the barrel depend critically on the surface tensions of molten solder in relation to the solder interface with component terminals and copper plated holes. Upon discovering of the root causes, then, appropriate engineering solutions are to be implemented, be it equipment upgrade, board re-design, process adjustment or material changes. The course aims to provide a concise description of these factors through simplified notes, shared experiences and interaction in class.
Why Should You Attend:
- There will be adequate time to have our industry experts respond to your questions
- Networking time will allow you to continue discussions following the presentations
- This is one of the best ways to enhance your knowledge and your company's profitability
- Extensive participation from experts from around the world provides for a comprehensive educational experience
- The SMTA reputation ensures high quality technical information that can be put to use immediately