Silicon Valley (San Jose)San Jose, CA
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June 1 Coplanarity & Warpage Technical Meeting
The SMTA Silicon Valley cordially invites you to attend:
Warpage & Their Effects & Ramifications for Assembly Reliability
arpage Effects on Flip Chip BGA Solder Joint Quality
Raiyo Aspandiar and Jagadeesh Radhakrishnan,
Abstract: Impact of excessive dynamic warpage on BGA solder joint quality
Biographies: Raiyo Aspandiar is a Senior Process Development Engineer at Intel, Hillsboro, Oregon, with over 32 years’ tenure at Intel. His fields of expertise include solder metallurgy, SMT process and solder joint defect analysis. Raiyo is a member of the Board of Directors of SMTA and he is Chair of the iNEMI Board Assembly TIG.
Jagadeesh Radhakrishnan is a Senior Quality Reliability Engineer at Intel, Folsom, California. He received his Bachelor’s in Technology in Mechanical Engineering from the Indian Institute of Technology, Madras, and Master’s in Mechanical Engineering from the University of Maryland, College Park, specializing in Electronic Packaging. His areas of interest include thermo-mechanical analysis, design, modeling and testing of semiconductor packaging technology for component, board and system level applications. He is an active participant in IPC/JEDEC, iNEMI and SMTA
PCB Warpage During Reflow & Effect
on PCBA Yield
Ryan Curry, Akrometrix
Abstract: PCB warpage has been identified as one of several key contributors to unacceptable yield rates during reflow assembly of a PCB module to a PCB carrier board. In an effort to improve attachment yield rates, a design of experiments was performed to evaluate several PCB design variables that are believed to contribute to warpage during reflow, including: 1) laminate material; 2) layer-to-layer copper balance; 3) panel configuration of the 6-up module array; and 4) location of the 6-up array in the PCB fabricator’s working panel. To simplify the investigation, only the variables associated with module PCBs are considered; the carrier PCB design is held constant. Additional graphical and statistical data that shows real-time at-temperature warpage behavior of several PCB modules and carriers will also be presented. This includes a detailed at-temperature gap analysis that shows the co-planarity gap between module and carrier at each critical reflow temperature.
Biography: Ryan Curry is a Technical Account Manager at Akrometrix. He is a subject matter expert in temperature warpage and strain measurement. Ryan has a mechanical engineering degree from Georgia Institute of Technology
Effects of Warpage on SMT Printing & Placement Process
Mark Ogden, ASM Assembly Systems
Abstract: Discussion of the factors that cause board warpage prior to printing and SMT placement. Examples of defects caused by board warpage will be discussed and explanations given on the mitigation measures that can be taken in the printer and pick and place machines
Biography: Mark Ogden is a Senior Marketing Manager at ASM Assembly Systems. Serving 25 years with the company, Mark's role is to plan and manage all customer marketing events in the Americas region, including trade shows, road shows and technology events. Mark began his career as a SMT production engineer at Siemens in Germany. Since then he has held various management roles in Europe and the United States. Mark has engineering degree from the University of Bath in the UK.
Thursday, June 1, 2017
2090 Fortune Drive
San Jose, CA
Topic: Coplanarity & Warpage and their Effects and Ramifications for Assembly Reliability
CLICK HERE TO RSVP TODAY!
Watch this spot for more info regarding the agenda and speakers for this meeting, but meanwhile, please hold the date on your calendar.
Sillicon Valley SMTA Technical Conference and Expo
DATE: Wednesday November 29, 2017
2090 Fortune Drive, San Jose, CA 95131
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|Date / Time||Event||Location||Phone||Contact/Email|
June 1, 2017
|Coplanarity and Warpage effects||Bestronics||408-234-9485||
September 15, 2017
|SMTA Golf Tournament||Spring Valley Golf Course Milpitas||(408) 456-1536||
October 12, 2017
|Ruggedization of Electronics,||TBD||408-234-9485||
November 29, 2017
|Technical Conference and Expo||Bestronics, San Jose||408-234-9485||
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