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Chapter News

SMTA Capital Expo to Feature Essemtec Fox Pick and Place System

 August 16, 2017 - The SMTA Capital Chapter is pleased to announce that it will feature a live demo of the Essemtec Fox pick-and-place system at the upcoming expo on Thursday, August 24th.  
 
The Essemtec Fox can have up to 180 feeder lanes, needs only 1sqm of floor space and can accept PCBs of up to 406 x 305 mm. It is expandable in any direction. The Fox can drive up to 180 feeder lanes, illustrating its dedication to high-mix production. Due to its small footprint and reasonable weight, the machine is ideal for use in limited space production areas even those located on upper floors.
 
The SMTA Capital Expo and Tech Forum will be held at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, 11100 Johns Hopkins Road, Laurel, MD 20723. Registration opens at 8:00 AM and includes a complimentary lunch on the show floor.  Exhibits are open from 9:00 AM until 3:00 PM and the first technical presentation will start at 9:30 AM.
 
Please join us for this great networking and free educational event.  To register online to attend or exhibit, please visit http://www.smta.org/expos/#capital.






Shannan O’Shaughnessy, GVD Corporation, to Present at SMTA Capital Chapter’s Expo and Tech Forum

 August 11, 2017 - The SMTA Capital Chapter is pleased to announce that Shannan O’Shaughnessy of GVD Corporation, will present “Reliability without Hermeticity: Commercial Vapor Deposited Coatings for High-Frequency RF Micro-Electronics” at the upcoming Capital Expo and Tech Forum at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, on Thursday, August 24th.  
 
Radio frequency (RF) micro-electronics are used everywhere in today’s technology, from the internet of things to military radar systems. It is challenging for these advanced RF systems to meet size, weight, power and cost requirements set by consumer market or defense agency demand, what the military calls “SWaP-C”, due to the need for packaging of the RF components and integrated circuits (ICs) in to ensure long term reliability. Reliability concerns traditionally necessitate the environmental protection of these high-frequency RF devices at either the component or the assembly level by hermetically sealing the device in a bulky, heavy expensive metal enclosure to prevent degradation caused by hazards in device operating environments. Industry standard conformal coatings are unusable due to the significant signal degradation which occurs if applied directly over an RF circuit. There is a critical need for a coating alternative to which is compatible with high-frequency RF devices to provide a lower weight and lower volume environmental protection scheme with high reliability and negligible performance impact for RF devices. This approach would allow RF device integration on size, weight, and cost effective PCBs and eliminate the hermetically packaged chip-and-wire assemblies currently in use. To address this need, GVD Corporation has developed a high reliability environmental coating, Exilis, for RF electronics devices that can be applied to both the bare device and completed assemblies. 
 
The SMTA Capital Expo and Tech Forum will be held at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, 11100 Johns Hopkins Road, Laurel, MD 20723. Registration opens at 8:00 AM and includes a complimentary lunch on the show floor.  Exhibits are open from 9:00 AM until 3:00 PM and the first technical presentation will start at 9:30 AM.
 
Please join us for this great networking and free educational event.  To register online to attend or exhibit, please visit http://www.smta.org/expos/#capital.






Gerry Partida, Summit Interconnect, to Present at SMTA Capital Chapter’s Expo on August 24th

August 3, 2017 - The SMTA Capital Chapter is pleased to announce that Gerry Partida of Summit Interconnect, will present “Density, Advanced Materials and Cost Drivers Associated with Advanced Circuit Design, Fabrication and Assembly” at the upcoming Capital Expo and Tech Forum at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, on Thursday, August 24th.  
 
Printed circuit boards are the platform for all surface mount technology processes and electronics manufacturing. There have been tremendous advancements in high speed and microwave materials, via structures and processing techniques. The material constructions and attributes provide unique opportunities for designers and unique challenges for bare printed circuit board fabricators. Mr. Partida will explore the various material options and their trade-offs, provide insight into the manufacture of multiple lamination cycle requirements, review stack-up and routing considerations, managing registration requirements, micro drilling and copper wrap plating processes. This will be an invaluable session to understand materials considerations, cost trade-offs and leading-edge processing technologies for the design, manufacture and assembly of high-technology printed circuit boards.
 
The SMTA Capital Expo and Tech Forum will be held at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, 11100 Johns Hopkins Road, Laurel, MD 20723. Registration opens at 8:00 AM and includes a complimentary lunch on the show floor.  Exhibits are open from 9:00 AM until 3:00 PM and the first technical presentation will start at 9:30 AM.
 
Please join us for this great networking and free educational event.  To register online to attend or exhibit, please visit http://www.smta.org/expos/#capital.






Phil Zarrow, ITM Consulting, to Present at SMTA Capital Chapter’s Expo and Tech Forum on August 24th

July 27, 2017 - The SMTA Capital Chapter is pleased to announce that Phil Zarrow of ITM Consulting, will present “The ‘Deadly Sins’ of SMT Assembly” at the upcoming Capital Expo and Tech Forum at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, on Thursday, August 24th.  
 
Everyone has heard of the “7 Deadly Sins” that will, supposedly, lead one to Hell. There are also the “Deadly Sins” of SMT - there are more than just 7 – and they can make your assembly process a “hell on earth”.
 
During the course of ITM’s assembly process audits and troubleshooting work, we tend to see trends in the types of errors and problems. In other words, a lot of people are making the same mistakes. The resulting process problems wreak havoc with an impact on assembly yields ranging from 5 to 20%. In addition to this direct cost, there is also additional financial impact with regard to time spent reworking and repairing, the on corrective action by QC, Engineering and Management, and, of course, “do-over”.
 
This presentation identifies the “deadly sins” of SMT assembly, both for Pb-free and “leaded” processes. Besides the symptoms and consequences of each type of error, root-cause, rectification and prevention techniques will be presented. Best Practices will be discussed for each of the key process steps. The workshop will, thus, provide the participant with an understanding of how to identify and correct the most common SMT assembly problems. It will include identification of vendor and source problems including components and materials as well as design related problems.
 
The SMTA Capital Expo and Tech Forum will be held at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, 11100 Johns Hopkins Road, Laurel, MD 20723. Registration opens at 8:00 AM and includes a complimentary lunch on the show floor.  Exhibits are open from 9:00 AM until 3:00 PM and the first technical presentation will start at 9:30 AM.
 
Please join us for this great networking and free educational event.  To register online to attend or exhibit, please visit http://www.smta.org/expos/#capital.
 






SMTA Capital Chapter’s Expo and Tech Forum to be Held on August 24th

July 10, 2017 - The SMTA Capital Chapter is pleased to invite you to its upcoming Capital Expo and Tech Forum at Johns Hopkins University / Applied Physics Lab, Kossiakoff Center, 11100 Johns Hopkins Road, Laurel, MD 20723, on Thursday, August 24th

During this year’s expo, the Capital Chapter will host technical presentations by ITM Consulting, Summit Interconnect, and GVD Corporation. Specific topics include “The “Deadly Sins” of SMT Assembly,” “Density, Advanced Materials and Cost Drivers Associated with Advanced Circuit Design, Fabrication and Assembly,” and “Reliability without Hermeticity: Commercial Vapor Deposited Coatings for High-Frequency RF Micro-Electronics.”

Registration opens at 8:00 AM and includes a complimentary lunch on the show floor.  Exhibits are open from 9:00 AM until 3:00 PM and the first technical presentation will start at 9:30 AM.

Please join us for this great networking and free educational event.  To register online to attend or exhibit, please visit http://www.smta.org/expos/#capital.






Second Meeting of 2017 - April 25 at ZESTRON Americas

Presentations at the second meeting of the year for the SMTA Capital Chapter held at ZESTRON Americas included:

Dr. Gil Sharon, DfR Solutions, presented “Effective Use of Reliability Simulation in an Agile Development Process”.

The use of simulation to predict reliability early in development is increasing as more electronic equipment manufacturers migrate to an Agile Methodology. However, most companies struggle to incorporate simulation and modeling successfully into new product introduction. This presentation will outline industry best practices in regards to the timing and workflow for the integration of reliability simulation and modeling. The audience will be introduced to process flows appropriate for component selection, pre-layout and post-layout activities. The type and timing of data transfer will be discussed and how it can be adjusted for different corporate structures. Case studies relevant to Solid State Drives (rigorous requirements for temp cycle, shock and vibration), Internet of Things (small form factor, state-of-the-art wireless, uncontrolled environments), and rapid implementation of Advanced Packaging (small pitch, large die, 3D) into Automotive and Military applications will be presented. There is a specific focus on the value of iteration and tradeoff studies generated by an integrated reliability simulation.

Naveen Ravindran, ZESTRON Americas, presented “High-Reliable Cleaning Process Optimization & Customer Requirements”.

Product quality is vital to manufacturing products that meet the customer’s reliability standards. However, when new customer requirements cannot be met, line deficiencies must be identified and corrected. Mr. Ravindran will provide details on how a properly designed experiment unveiled the solutions to a customer’s cleaning challenges and identified a way to increase product quality while decreasing operating costs.

To request a copy of the presentations, contact Jessica Kreis, VP of Communications at j.kreis@zestronusa.com.






We want to hear from you about SMT Processes Certification

The SMTA Certification Committee is looking for feedback about the existing SMT Processes Certification Program. It takes less than 2 minutes to provide your input about the potential of running a program in the DC area.

Take the survey here!






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The SMTA Capital Chapter is looking for sponsors to advertise in our newsletter.  Advertising revenues will help the Capital Chapter to bring the best experts to our meetings and workshops.  Please, contact Fernando Rueda (fernando_rueda@kyzen.com) for details.






Chapter Calendar of Events
Date / Time Event Location Phone Contact/Email
February 23, 2017
5:00
SMTA Capital Chapter to Host First Meeting of the Year The Test Connection (410) 205-7300   Bert Horner 
whornerttci@gmail.com
April 25, 2017
5:30 pm
MTA Capital Chapter to Host Second Meeting of the Year ZESTRON Americas 703-393-9880   Jessica Kreis 
j.kreis@zestronusa.com
August 24, 2017
Vendor-Expo - Capital 2017 Johns Hopkins University/Applied Physics Lab   Kaitlyn Gherity 


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Our Chapter Leaders

President : Brian A. Costanzo  (DRS Signal Solutions)
Phone : 301-944-8535
Email : briancostanzo@yahoo.com

Vice President : Karen Walters Ebner  (Raytheon Systems Company)
Phone : 443-558-5332
Email : karen_ebner@raytheon.com

Secretary : Bert Horner  (The Test Connection, Inc.)
Phone : 410-205-7300
Email : whornerttci@gmail.com

Treasurer : Fernando Rueda  (KYZEN Corporation)
Phone : 615-983-4603
Email : fernando_rueda@kyzen.com

VP of Technical Programs : John Vaughan  (Zentech Manufacturing, Inc.)
Phone : 443-348-4500
Email : vaughanj@zentech.com

VP of Membership : Tom O'Connor  
Phone : 410-730-3385
Email : tomfoc3@gmail.com

Acting VP of Communications : Larry Park  (ZESTRON Americas)
Phone : 703-393-9880
Email : Lawrence.Park@zestronusa.com

Board Liaison : Sal Sparacino (ZESTRON Americas)
Phone Contact : 703-393-9880
Email Address : s.sparacino@zestronusa.com

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Global Members of our Chapter

ZESTRON Americas



Global Participating Members of our Chapter

Harris Corporation

KYZEN Corporation

ZESTRON Americas

ZESTRON Americas



Corporate Members of our Chapter

Annapolis Micro Systems, Inc.

Apex Factory Automation

CEMSI

Cornet Technology

Department of Defense

Leidos

NTS-Baltimore

Practical Technologies, Inc.

Simplimatic Automation

The Test Connection, Inc.

Zentech Manufacturing, Inc.

ZESTRON Americas



SMTA Global Members

Amazon Celestica Inc. Cisco Systems, Inc. Creation Technologies Inc. FCA Group Harris Corporation Henkel Electronic Materials LLC HISCO, Inc. IDENTCO ITW EAE Jabil Circuit Sdn. Bhd. Keysight Technologies KYZEN Sdn. Bhd. Metallic Resources, Inc. Micro Systems Technologies Management AG NCAB Group USA NEO Technology Solutions Plexus Corp. Samtec Microelectronics SMAC Specialty Coating Systems Vexos ZESTRON Americas

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