SMTA International  

Conference: Sep. 28 - Oct. 2, 2014  
Exhibition: Sep. 30 - Oct. 1, 2014  

Donald Stephens Convention Center  
Rosemont, IL  


Half day (3.5 hours) educational courses are led by internationally respected professionals with extensive experience in the subject area. Course instructors deliver focused, in-depth presentations on topics of current importance to the industry, based on their research and industry experience. Tutorials are application oriented and structured to combine field experience with scientific research to solve everyday problems. Tutorials are offered on Sunday, Monday, and Thursday to provide you the opportunity to attend the conference sessions and visit the exhibit floor.

Tutorial registration includes breaks, course materials, and a Certificate of Attendance.
Biographies for all instructors are available.

  • Advanced Packaging
  • Substrates
  • Manufacturing and Assembly
  • Monday
  • Manufacturing and Assembly
  • Quality and Reliability
  • Soldering
  • Thursday
  • Substrates - FREE!

  • SUNDAY, October 13



    Advanced Component Packages & Processes

    S. Manian Ramkumar, Ph.D., Rochester Institute of Technology
    Sunday, October 13 | 8:30am – 12:00pm | Room 104A-B

    Course Objectives
    This workshop will identify and categorize the advanced components packages, their nomenclature and construction, and packaging trends. Discussions will relate to miniature and embedded passive technologies, their assembly process, and IC packaging technologies. Participants will be provided an understanding of substrates, substrate requirements, and means for thermal management with advanced packages. Benefits and issues of various advanced IC packages including the assembly process requirements will be introduced. Specific packages to be discussed include Quad Flat Pack No Lead (QFN), Area Array Packages (BGAs, CSPs, Wafer Level CSPs, Package-on-Package, CGAs and Flip Chips), and Multi Chip Modules (MCM). A brief discussion of equipment requirements for advanced component assembly will also be included.

    Topics Covered

    1.) Introduction

    2.) Electronics Packaging & Levels

  • What is electronics packaging?
  • Levels of Electronics Packaging
  • Thermal Management
  • Substrate Properties

    3.) Active SMT Components

  • Active Component Types
  • Active Component Configurations
  • Active Component Specifications
  • IC Packaging Trends
  • Package Evolution
  • Factors Influencing the Package Evolution

    4.) Ball Grid Array (BGA) Packages

  • Why are BGAs so popular?
  • Manufacture of BGAs
  • BGA Configurations

    5.) Plastic BGAs

  • Component Construction & Details
  • Plastic BGA Benefits & Issues
  • Self-Centering of PBGAs

    6.) Ceramic BGA (CBGA)

  • Component Construction & Details
  • Ceramic BGA Benefits & Issues

    7.) Tape BGA (TBGA)

  • Component Construction & Details
  • Tape BGA Benefits & Issues

    8.) Super BGA

  • Component Construction & Details

    9.) Chip Scale Packaging (CSP)

  • CSP Types
  • CSP Packages
  • CSP Packaging for Automated Assembly
  • Factors Influencing Increased Interest in CSP Packages

    10.) Wafer Level Packaging & I/O Redistribution

    11.) Package-on-Package (PoP) Assembly

    12.) Flip Chip Attach

  • What is flip chip?
  • Flip Chip Attach-Size Advantage
  • Flip Chip Bumping
  • Flip Chip Packaging for Assembly
  • Flip Chip Assembly Process
  • What is Encapsulation?
  • Flip Chip Attach-Benefits
  • Flip Chip Attach-Issues

    13.) Ceramic Column Grid Array (CCGA)

  • Component Construction & Details
  • CCGA Solder Joint-Thermal-Fatigue-Induced Failure

    14.) Multi-Chip-Module (MCM)

  • MCM Constructions
  • Benefits & Issues

    15.) System-In-Package (SIP)

    16.) MEMS Packaging


    3D Packaging, Interconnect, and Assembly

    Charles Bauer, Ph.D., TechLead Corporation
    Sunday, October 13 | 1:30pm — 5:00pm | Room 103B

    Course Objectives
    After more than a decade the industry continues to recognize the power of the third dimension in package, sub-system and system assembly for the implementation of highly integrated electronic products. 3D assembly and packaging of both active and passive devices opens a new world of performance and integration to system designers. Numerous approaches reported and demonstrated include those based on package stacking (package-on-package, origami, and edge stacked modules) and those based on die stacking (wire bond, mixed technology, edge redistribution, interposers, and through-silicon-via or TSV).

    TSV and interposer technologies stand out from the others as 3D device integration approaches as opposed to 3D packaging methods. Consequently, through silicon via technology and interposers present unique opportunities and challenges. For example, TSVs promise unrivaled performance improvements due to short, low impedance interconnect and high silicon efficiency. On the other hand, no other 3D approach disrupts the existing supply chain so dramatically.

    Updated annually to include the latest developments, this course covers both fundamental and advanced technologies that today produce stacked chip packages and assemblies as well as stackable packages for implementation of highly integrated electronic products. These include the challenges of die thinning, thin die handling and attachment, multi-level wire bonding, mixed technology die attachment and bonding, flip chip, TAB and TSV technologies. Substrate selection for various 3D packaging techniques including silicon tiles, flex circuit origami and specialty interposers concludes the chip stacking section of the course. Several examples of specific 3D package structures demonstrate both the power and limitations of these approaches.

    Package on Package (PoP) SMT assembly processes include flux dip and paste dip, the challenges of fine pitch printing, placement and reflow of PoP packages and warpage control in multi-level packages inspection and rework of multilevel package assemblies. The instructors also identify common defects occurring in PoP and 3D package assembly such as head-on-pillow, no-wet opens, chip flex, etc. as well as their prevention and repair.

    Further considerations for 3D electronics include stackable packages based on flex and rigid substrate approaches, integrated system-in-package techniques and multilayer, embedded passive technologies. Additional coverage of SMT design and assembly implications rounds out the technical content of the course. Using multiple examples of 3D packages in actual usage today, the course also presents a review of the drivers, economics, and intellectual property landscape behind 3D packaging.

    Topics Covered

  • 3D History, Trends & Drivers Packaging
  • Conventional Die Stacking
  • Assembly process guidelines for BTC
  • Through Silicon Vias
  • Integrated Passives Interconnection
  • Major design considerations for BTCs
  • Substrates
  • Interposers Enabling Technologies Package on Package (PoP)
  • SMT Stacked Packages
  • Printing
  • Placement
  • Dip
  • Reflow
  • PoP Underfill
  • PoP Rework failure analysis techniques
  • PoP inspection
  • Common PoP defects 3D Applications Economics of 3D (Confusing, ask Chuck about this one?)
  • Integration
  • Chip Stacking/TSV versus PoP Intellectual Property Landscape for 3D Packaging

    SUBSTRATES - Sunday


    Electrochemical Migration and Conductive Anodic Filament (CAF) Formation

    Laura Turbini, Ph.D., International Reliability Consultant
    Sunday, October 13 | 8:30am — 12:00pm | Room 202C

    Course Objectives
    Electrochemical migration (ECM) is the movement of an ionic species under the influence of a DC voltage. This course will present the factors which affect ECM and the failure modes that it can produce. Test methods that will be discussed include surface insulation resistance (SIR), electrochemical migration (ECM) and a quantitative copper corrosion test, developed by Dr. David Bono and modified by the presenter. A special case of ECM is CAF formation. This failure mode will be discussed in detail and the chemistry of the filament will be explained. The effect of processing chemicals, board design, etc. will also be included.

    Topics Covered

  • Electrochemical migration (ECM) and the factors which accelerate it
  • Failure modes associated including surface dendrites, subsurface conductive anodic filament formation and open circuit failure
  • Relevant test methods including surface insulation resistance (SIR), ECM, and a new copper corrosion test
  • Conductive Anodic Filament (CAF) formation
        a.Historic Perspective
        b.Impact of processing temperature, substrate, materials and processing chemicals
        c.Effect of today’s high density boards d.Chemistry of CAF formation


    Design and Assembly Process Principles for Flexible and Rigid Flex Circuits

    Vern Solberg, Invensas Corporation
    Sunday, October 13 | 8:30am — 12:00pm | Room 103A

    Course Objectives
    The design guidelines for flexible circuits, although similar to rigid circuits, are somewhat unique. In essence, flex-circuits furnish unlimited freedom of packaging geometry while retaining the precision density, and repeatability of printed circuits. Flex-circuits typically replace the common hard-wire interface between electronic assemblies. The flexible circuits, however, have significant advantages over the hard-wired alternative because they fit only one way, eliminate wire routing errors, and save up to 75% on space and weight. Because the flex-circuit conductor patterns can maintain uniform electrical characteristics they contribute to controlling noise, crosstalk, and impedance. The flex-circuits will often be designed to replace complex wire harness assemblies and connectors to further improve product reliability.

    During the workshop program participants will have an opportunity to review and discuss base material sets, alternative fabrication methodologies and SMT-on-flex assembly processes. The workshop will also include practical supplier recommendations for ensuring quality, reliability and manufacturing efficiency.

    Topics Covered
    1. Applications and use environment

  • Commercial/Consumer
  • Industrial/Automotive
  • Medical/Aerospace
  • 2. Material and component selection

  • IPC standards for flex and rigid-flex dielectrics
  • Base material and metallization technologies
  • Selection criteria for SMT components
  • SMT land pattern development

    3. Design guidelines for flexible and rigid-flex circuits

  • Flex circuit outline planning
  • Circuit routing and interconnect methodologies
  • Fold and bend requirements
  • SMT land pattern reinforcement criteria

    4. Assembly processing of flex and rigid-flex circuits

  • Dimensioning and tolerance criteria
  • Palletized layout for in-line assembly processing
  • SMT assembly process variations and methodologies
  • Alternative joining methods for flexible circuits



    SMT Process Fundamentals for Tin-Lead and Lead Free Assembly

    S. Manian Ramkumar, Rochester Institute of Technology
    Sunday, October 13 | 1:30pm — 5:00pm | Room 104A-B

    Course Objectives
    This course will provide an introductory but holistic understanding of the surface mount and mixed technology assembly processes for lead based and lead free electronics packaging. Topics include PCBs, assembly types, component types, assembly process, assembly materials, identification of defects, troubleshooting and process control. Design for ease of manufacture and assembly will be discussed throughout the lecture. Tradeoff decisions between different materials and equipment types will also be highlighted. A comparison of lead based and lead free process will be provided, including implementation issues.

    Topics Covered
    1.) Electronics Packaging & Levels

  • Functions of Packaging
  • Thermal Management Issues
  • PCB Packaging
  • Assembly Types
  • Assembly Process Sequence

    2.) PCB Types, Materials and Manufacturing

    3.) Overview of Through Hole Technology

  • Component Types & Process Steps

    4.) Overview of Surface Mount Technology

  • Passive Component Types
  • Active Component Specifications
  • Active Component Types (ICs)
  • Common SMT assembly process

    5.) Stencil Printing

  • Solder Paste-Characterization, Types, Handling & Safety
  • No-Lead Solder and its Impact
  • Stencils and Squeegees-Materials, Types & Manufacturing
  • Print Parameters
  • Process requirements for Lead Free
  • Print Characteristics, Defects and Corrective Action

    6.) Adhesive Dispense

  • Adhesive Types, Selection & Dispensing Techniques
  • Inspection
  • Reflow Curing

    7.) Component Placement

  • Factors Influencing the use of Automated Placement Equipment
  • Machine Configurations & Types
  • Component Packaging for Automated placement

    8.) Soldering

  • Reflow Soldering
  • Typical Reflow Profile
  • Profiling & its importance-How to?
  • Factors affecting good reflow
  • Lead Free Solder and Profiling Changes
  • Wave Soldering
  • Changes needed for Lead Free Solder
  • Process Sequence & Defects

    9.) Cleaning Materials, Process, & Testing for cleanliness

    10.) Inspection Techniques, Assembly Defect Identification and Corrective Action

    11.) Testing of PCB Assemblies

    12.) Rework and Repair


    The “Deadly Sins” of SMT and Lead-Free Assembly

    Phil Zarrow and Jim Hall, ITM Consulting
    Sunday, October 13 | 1:30pm — 5:00pm | Room 103A

    Course Objectives
    Everyone has heard of the “7 Deadly Sins” that will, supposedly, lead one to Hell. There are also the “Deadly Sins” of SMT - there are more than just 7 – and they can make your assembly process a “hell on earth”.

    During the course of our assembly process audits and troubleshooting work, we tend to see trends in the types of errors and problems. In other words, a lot of people are making the same mistakes. The resulting process problems wreak havoc with an impact on assembly yields ranging from 5 to 20%. In addition to this direct cost, there is also additional financial impact with regard to time spent reworking and repairing, the on corrective action by QC, Engineering and Management, and, of course, “do-over”.

    This workshop identifies the “deadly sins” of SMT assembly, both for Pb-free and “leaded” processes. Besides the symptoms and consequences of each type of error, root-cause, rectification and prevention techniques will be presented. Best Practices will be discussed for each of the key process steps. The workshop will, thus, provide the participant with an understanding of how to identify and correct the most common SMT assembly problems. It will include identification of vendor and source problems including components and materials as well as design related problems.

    Topics Covered

  • Areas of General Process "Sins"
  • Utilization of Process Feedback Data
  • Design for Manufacturability and Assembly
  • In-Process Inspection and AOI
  • Solder Paste Selection
  • MSD
  • Procedures and Documentation

    MONDAY, October 14



    SMT Manufacturing: Preventing Production Defects and Failures – Part 1

    Jennie Hwang, Ph.D., H-Technologies Group
    Monday, October 14 | 8:30am — 12:00pm | Room 202C

    Course Objectives
    Considering the new and anticipated developments in packaging and assembly, to set the goal to achieve high yield production and to produce reliable products, this course addresses the prevalent issues occurring on the production floor, which likely decrease the yield, increase the cost and jeopardize reliability. The course focuses on “how-to” prevent the issues and take remedial measures through the understanding of potential causes. Specific defects associated with BTCs and PoPs will also be outlined. The morning session (Part 1) will discuss the deficiencies and defects related to solder joints and soldering, and the issues related to components and PCB bare board will be discussed in the afternoon session (Part 2). Attendees are encouraged to bring their concerns for discussion.

    Topics Covered

  • Solder joint void (is solder joint void an issue, what are various sources, how to minimize voids and what are acceptance criteria?)
  • Solder joint surface crack (is it a reliability issue? what are causes and can it be avoided?
  • Solderability (how to achieve optimal wetting and what are the differences between Pb-free and SnPb in wetting?)
  • Solder balling and beading (what are causes and how to minimize them?)
  • Cold solder joint (what are key factors of cold solder joints?)
  • Starved solder joint (what are root causes of starved solder joint and mitigation measures?)
  • Open solder joint (What are root causes of open joint and mitigation measures?)
  • Head-on-pillow defect (what are potential causes, factors, remedies?)
  • Copper dissolution (what are factors and remedies? What is the impact on thru-hole solder joint reliability?)
  • Through-hole barrel filling (what are process parameters to achieve optimal filling?)
  • Wave and selective soldering issues (what are likely issues and solutions related to wave soldering and selective-wave-soldering? and solutions?)
  • Black pad (what are causes and remedies of Black pad?)
  • Pb-contamination (what is considered to be the threshold?)
  • Defects of BTC solder joints (prevention and remedies)
  • Defects of PoP solder joints (prevention and remedies)


    Design and Assembly Process Challenges for Bottom Terminations Components (BTCs) such as QFN, DFN and MLF in Tin-Lead & Lead Free World

    Ray Prasad, Ray Prasad Consultancy Group
    Monday, October 14 | 8:30am — 12:00pm | Room 104A-B

    Course Objectives
    Bottom Termination surface mount Components (BTCs) go by various names such as QFN, DFN, SON, LGA, MLP, and MLF, which utilize surface to surface interconnections. BTCs are like BGAs but without the balls. This minor difference in the physical I/O shape makes all the difference in design, assembly and rework between BTCs and BGAs.

    Since there are no leads or balls in BTCs to take up any slack from package or board warpage, you essentially need perfection in design and assembly process. When was the last time you saw everything perfect on any manufacturing floor?

    One must also keep in mind that these parts are not the only components that must be mounted on the board. Look at any board. It will have other packages such as BGAs, fine pitch and even some through-hole components; and those components have their own unique design and assembly implementation requirements. So designing for BTCs may involve trial and error and lot of frustration by many companies. Additional frustration is caused by fast-paced changes in packaging technologies and the advent of Lead Free has compounded the designer’s task.

    When it comes to inspection, BTCs pose even more challenge than BGAs. What you may see in visual inspection may look bad but may really be acceptable. And what you don’t or can’t see may really be critical. And the fact that the Process Engineer must worry about both too much solder and too little solder on the same BTC package makes the quality engineer nervous about field returns.

    The objective of the course is to get away from the trial and error approach and provide you successful design and process practices commonly used by the industry. This course will cover the practical details of BTC design and assembly processes. This course is based on Surface Mount Technology: Principles by Ray Prasad and Practice and IPC 7093 Design and Assembly Process Guidelines for BTCs also co-chaired Ray. This course identifies many of the characteristics that influence the successful implementation of robust and reliable BTC assembly processes.

    This is not a theoretical course. It Is based on Mr. Prasad's over two decades of experience at Boeing, Intel and numerous clients and deals with "real-world" problems in lead free and tin-lead BTC implementation.

    Topics Covered

  • Pros and Cons of BTC
  • Pull Back Vs Non Pull Back
  • BTC Package Manufacturing Process

    Major Design Considerations for BTCs

  • Laminates and Surface Finish Considerations
  • Land Pattern and Stencil Design Guidelines
  • Component considerations

    Assembly Process Guidelines for BTC

  • Solder Paste Printing- the Key Process Step
  • Reflow Process Guidelines
  • BTC Solder Joint Quality Requirements
  • BTC Rework Process

    Key strategies in design and manufacturing processes to prevent field returns


    Design for Manufacturing (DFM): Impacts to Achieving High Yield Process with Today's PCB and Component Packaging

    Dale Lee, Plexus Corp.
    Monday, October 14 | 1:30pm — 5:00pm | Room 104A-B

    Course Objectives
    Today’s PCB and assembly design tolerances, materials and component packaging technologies have impacted traditional assembly processes with very tight solder application, component placement and soldering constraints. Using traditional assembly and soldering process controls are insufficient to achieve a high yielding manufacturing process. This course will introduce the element of matching the assembly/soldering process to the requirements in the product design. Examples of several opportunities within this process for yield improvement through manufacturing tooling design, SMT and PTH assembly process matching and environmental controls that can impact manufacturing yields will be presented.

    Topics Covered

  • Global Product Design Elements
  • PCB Design Impacts
  • Wave Solder Design Impacts
  • SMT Solder Design Impacts
  • Thermal Balance, Trace Routing, Equipment Limitation/Tolerance, PCB/PCB Array Tolerance, Process Tooling Design
  • Process Control Impacts
  • Paste Volume, Thermal Shock SMT & PTH, Reflow Process Warpage
  • Cleaning Impacts
  • Assembly and Test Compatibility Issues: Low Stand-off Components, PCB Construction, Test Point Density, Next Higher Assembly


    SMT Manufacturing: Preventing Production Defects and Failures – Part 2

    Jennie Hwang, Ph.D., H-Technologies Group
    Monday, October 14 | 1:30pm — 5:00pm | Room 202C

    Course Objectives
    Considering the new and anticipated developments in packaging and assembly, to set the goal to achieve high yield production and to produce reliable products, this course addresses the prevalent issues occurring on the production floor, which likely decrease the yield, increase the cost and jeopardize reliability. The course focuses on “how-to” prevent the issues and take remedial measures through the understanding of potential causes. Specific defects associated with BTCs and PoPs will also be outlined. The morning session (Part 1) will discuss the deficiencies and defects related to solder joints and soldering, and the issues related to components and PCB bare board will be discussed in the afternoon session (Part 2). Attendees are encouraged to bring their concerns for discussion.

    Topics Covered

  • Tin whisker (what are the causes of tin whiskers and what are the practical solutions? What are the differences between tin whisker and tin pest?)
  • BGA solder ball drop (what are the implications of BGA solder ball drop under SAC solder paste reflow?)
  • BGA crack (how to control and mitigate BGA plastic package crack during reflow?)
  • BGA/CSP interposer heat damage (what is the primary cause?)
  • BGA/CSP co-planarity issue (what are remedies?)
  • BGA rework challenge (how to achieve successful rework for high-pin-count large BGAs?)
  • Ceramic chip capacitor damage (what are causes and preventive measures?)
  • SOT component cracks (what are mitigating measures?)
  • Tome-stoning (what are causes and remedies?)
  • 01001 component issue (what is the best practice?)
  • PCB board sagging (how to prevent it during reflow?)
  • PCB-related issues to watch (discoloration; de-lamination; blistering; PCB warp; Z-axis thermal expansion; intrinsic interconnect open; electro-migration; Cu-pad peel strength reduction; thru-hole barrel crack)
  • PCB Cu-pad lifting
  • PCB Pad cratering
  • Overall thermal damage (prevention)


    Implementing High Reliability Lead-Free Assembly and Test Methodology - NEW!

    Matt Kelly, IBM Corporation
    Monday, October 14 | 1:30pm — 5:00pm | Room 201C

    Course Objectives
    This course will discuss essentials for successfully implementing high reliability lead-free design, assembly, and test methodologies for use with high complexity, mission critical electronics. The course is intended for engineers responsible for the development and deployment of new material, assembly, and test technologies. Information provided represents over ten years of lead-free technology development and product migration execution. The goal of the course is to share multiple case studies to help engineers understand the bigger picture of what lead-free product conversion encompasses. The course content is timely for engineers developing high reliability products that may require a transition to lead-free assembly in the near future.

    All participants will receive the following documentation as a result of class enrollment:

  • Course overview & agenda
  • Presentation charts
  • Publications listing
  • Biography & contact information

    Topics Covered

    1. Lead-Free Product Conversion: Driving Forces and Strategic Approach

    2. Lead-Free Design for Manufacturability Considerations

  • DfX
  • Surface Insulation Resistance (SIR) Assurance

    3. Implementing High Complexity, High Reliability Lead-Free Assembly: A Recipe for Success

  • Product conversion elements
  • PCB review and qualification
  • Bill of materials review
  • Supplier process review
  • Mechanical hardware reviews
  • Lead-free readiness audits
  • Reliability qualification

    4. Advanced Lead-Free Technology Element Case Studies


  • PCB Survival and Qualification
  • Lead-Free HASL Surface Finish
  • Alternate Alloys
  • Halide-Free No-Clean Flux Chemistries
  • Water Soluble Lead-Free Chemistry

    Components and Temperature Limits

  • Temperature Sensitive Components and Risks
  • PTH Connector Temperature Mass Study
  • Lead-Free SMT Connector Assembly and Rework

    System Level Testing and Hardware Qualifications

  • Power Age/Power Cycling
  • Server Hardware Assembly Qualification

    5. Concluding Remarks / Successes, Remaining Challenges and Best Practices Summaries



    Failure Analysis: Lessons Learned in Manufacturing and Research

    Martin Anselm, Ph.D., Universal Instruments Corporation
    Monday, October 14 | 8:30am — 12:00pm | Room 103B

    Course Objectives
    Universal Instruments Corporation’s Advanced Process Laboratory has observed countless failures in electronics manufacturing. From fine pitch printing, to PoP and high Tg laminate failures. These failures combined with internal research have provided a unique perspective for design for manufacturability and reliability. These lessons will be presented to the class when we discuss material selection, current electronics research, and failure analysis case studies. We will touch on design considerations for many advanced assembly processes as well as discussing types of analytical techniques that can be used for materials characterization.

    Topics Covered

  • What the major difficulties in lead-free reliability testing are
  • Mixed alloy assembly best practices
  • PCB plating considerations
  • Analytical testing techniques and what they can identify root causes for production failures
  • Lead-free laminate selection and testing procedures: Can your board withstand 9x reflow?
  • Learned lessons from actual failure analysis case studies

    FA Tools and Techniques to be discussed include the following:

  • Thermogravimetric Analysis & IR
  • Ion Chromatography
  • Ion Contamination
  • Shadow Moire
  • Wetting Balance/Solderability
  • Acoustic Microscopy
  • White Light Interferometry
  • Mechanical Testing
  • Optical Microscopy
  • Mechanical Strain Gauge Analysis & Strain limits
  • X-Ray Inspection
  • Environmental Testing
  • Solder Paste Print Transfer Efficiency
  • Micro Hardness Testing
  • Dye Penetration Testing
  • Micro Sectioning
  • Cross-section Etching

    Suggestion: Bring specific questions or examples of surface mount process difficulties you are willing to share for an open discussion at end of class. In my experience many problems can be solved with a brief discussion of the issues.

    SOLDERING - Monday


    Soldering Technology for SMT: Achieving High Yields and Reliability

    Timothy Jensen, Indium Corporation
    Monday, October 14 | 8:30am — 12:00pm | Room 201C

    Course Objectives
    In this workshop, a detailed discussion of soldering materials, components, and PCBs will be given to help the attendee understand the important aspects of each to produce a complete electronics product that meets current and future legislative restrictions. Additionally, a detailed discussion of the assembly process will be covered with an examination of process optimization and defect elimination.

    Topics Covered

  • The Different Solder Alloy Systems (Cost and Reliability), How the Pb-Free Alloys Were Chosen, Trends Toward Alternative Alloys, The Importance of Dopants
  • How Solder Paste Selection Influences Profitability, Reliability, and Efficiency, Composition: Flux, Powder and the Many Additives, Powder Types, The Formation of Intermetallics, Sn/Pb vs. Pb-Free
  • Optimizing the Pb-Free Stencil Printing Process, Why 65% of Assembly Defects are From Printing, SMT Printing Fundamentals, Stencil Design, Achieving an Optimized Lead-Free SMT Printing Process
  • The Pb-Free Reflow Process , Lead-Free Reflow Differences, Ramp to Peak versus Soak Profiles, Achieving an Optimized Lead-Free SMT Reflow Process, Pb-Free SMT Defects: Causes and Solutions, Tombstoning, Graping, Head-In-Pillow, Voiding, Poor Wetting, Higher Temperature Issues
  • Through-hole Soldering Alternatives, Lead-Free Wave Soldering Process Fundamentals, Reliability vs. Hole Fill: J-STD-004B Dilemma, SAC vs SnCu Alloys, SMT Alternatives to Wave Soldering

    THURSDAY, October 17

    SUBSTRATES - Thursday

    FREE half day course for SMTA MEMBERS! You are required to register to receive a handout and a Certificate of Completion, but there is no charge for the course. (Non-member rate applies.)


    Design for Reliability for PCBs

    Cheryl Tulkoff, DfR Solutions
    Thursday, October 17 | 8:30am — 12:00pm | Room 104A-B

    Course Objectives
    Designing printed boards today is more difficult than ever before because of the increased lead free process temperature requirements and associated changes required in manufacturing. Not only has the density of the electronic assembly increased, but many changes are taking place throughout the entire supply chain regarding the use of hazardous materials and the requirements for recycling. Much of the change is due to the European Union (EU) Directives regarding these issues. The RoHS and REACH directives have caused many suppliers to the industry to rethink their materials and processes. Thus, everyone designing or producing electronics has been or will be affected.

    Topics Covered

  • Intro to Design for Reliability
  • DfR and Physics of Failure (PoF)

    Printed Circuit Boards

  • Laminated Selection
  • Plated Through Vias (PTVs)
  • Cracking and Delamination
  • PTH Barrell Cracking
  • CAF
  • Strain/Flexure Issues & Pad Cratering
  • Cleanliness
  • Electrochemical Migration
  • Surface Finishes

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