SMTA International  

Conference: Sep. 28 - Oct. 2, 2014  
Exhibition: Sep. 30 - Oct. 1, 2014  

Donald Stephens Convention Center  
Rosemont, IL  
 

Technical Sessions

Sessions are 1.5 hour programs in which three technical papers are presented under the direction of a chairperson. Each paper is presented by the author on a topic related to the main subject of the session, and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.

Session tracks and symposiums:
Advanced Packaging / Components (AAT)
Evolving Technologies (ET)
Conflict Minerals (EMS)
Harsh Environment Applications (HE)
Lead-Free Soldering Technology (LF)
Manufacturing Excellence (MFX)
Process Control (PRC)
SMT Assembly (SMT)
PCB Technology (SUB)
Monday
  • Evolving Technologies Summit
  • Harsh Environment Symposium
  • Tuesday
  • 11:00am - 1:00pm
  • 2:00 - 3:30pm
  • 4:00 - 5:30pm
  • Wednesday
  • 8:00 - 10:00am
  • 10:30am - 12:30pm
  • 2:00 - 3:30pm
  • 4:00 - 5:30pm
  • Thursday
  • Lead-Free Soldering Technology Symposium


  • Please note that speakers with a Speaker of Distinction icon are recognized as Speakers of Distinction. Over the past 15 years they have been identified by SMTAI attendees as giving the strongest technical presentations. Congratulations to each of these authors for a job exceptionally well done.



    MONDAY, September 29


    Evolving Technologies Summit
    FREE with a VIP or Technical Conference Registration!
    Organized by Reza Ghaffarian, Ph.D., Jet Propulsion Laboratories, Lars Böettcher, Fraunhofer IZM Berlin, and Steve Greathouse, Plexus Corp.
    Monday, September 29 | 8:30am - 5:00pm | Room 48




    ET1

    Embedded Technology

    Chair: Charles Woychik, Ph.D., Invensas Corporation
    Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratories
    Monday, September 29 | 8:30am - 10:30am | Room 48

    The goal of reducing size, weight, and power (SWaP) necessitates designs that increase functionality while, at the same time, further miniaturization. Embedded technology allows the designer to meet these objectives but, it is not without its challenges. This session examines advancements being made in the use of embedded components. The presentations will begin with an analysis of embedded passive devices that have had their use envelope extended to high frequency applications. Follow-on papers consider embedded active devices that include SiC and GaN for high-power assemblies. Device construction, circuit board materials, and interconnection technologies are all critical to the successful execution of embedded technologies in these more demanding applications.

  • PCB Design and Fabrication Process Variations for Embedding Passive and Active Components
    Speaker of DistinctionVern Solberg, Solberg Technical Consulting
  • Embedded Passive Technology Materials, Design and Process
    Hikmat Chammas, Honeywell
  • Power Overlay (POL) - Advanced Embedding Packaging Technology Platform
    Arun Gowda, Ph.D., Risto Tuominen, and Paul McConnelee, GE Global Research
  • Embedding of Power Semiconductors for Innovative Packages and Modules
    Speaker of DistinctionLars Böttcher, S. Karaszkiewicz and A. Ostmann, Fraunhofer IZM Berlin, and D. Manessis, TU Berlin



    ET2

    How Will Additive Manufacturing Effect Electronics Manufacturing?

    Chair: Irene Sterian, P.E., Celestica Inc.
    Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratories
    Monday, September 29 | 11:00am - 12:30pm | Room 48

    Additive manufacturing or 3D printing is rapidly changing the way we prototype and manufacture plastic and metal parts. Will electronics manufacturing be influenced and impacted by this disruptive technology? In this session, three presentations will explore the advances in printed electronics, whether incorporated into the 3D structures, or using new materials, and processes. Printed electronics may become as disruptive a technology, especially when combined with additive manufacturing.

  • Title TBD
    Dan Gamota and Girish Wable, Jabil Circuit, Inc.
  • Overview of Printed Electronics for PCB/SMT Industry
    Happy Holden, Gentex Corporation (Retired)
  • Turning Printed Circuit Boards Into Printed Circuit Structures Using 3D Printing
    Kenneth Church, Xudong Chen, Paul Deffenbaugh and Josh Goldfarb, nScrypt Inc.; Thomas Weller, University of South Florida.



    ET Keynote Lunch

    Chair: Reza Ghaffarian Ph.D., Jet Propulsion Laboratory
    Monday, September 29 | 12:30pm - 2:00pm | Room 48

  • Embedded Technology, Why Now?
    Jan Vardaman, TechSearch International, Inc.

    *To ensure an adequate number of lunches, you must pre-register in advance by checking "Evolving Technologies Summit" (Monday) on the registration form.



    ET3

    Understanding Your Next Generation Adhesives – Using Nano Fillers

    Chair: Steve Greathouse, Plexus Corp.
    Co-Chair: Lars Böettcher, Fraunhofer IZM Berlin
    Monday, September 29 | 2:00pm - 3:00pm | Room 48

    Conductive adhesives based on nano-technologies are revolutionizing the methods of connecting electronic materials and components by showing improved service temperature, thermal conductivity, electrical conductivity, and reliability. An overview of how nanoparticles can alter the mechanical properties (i.e., stiffness), electrical properties (i.e., conductivity), material properties (i.e., permeability, glass transition temperature), and fracture performance is outlined. Nano particles are in your future products. Come see how to start using them in your application.

  • Understanding Nano-Sized Fillers in Conductive Adhesives
    Herb Neuhaus, Ph.D. and Charles Bauer, Ph.D., TechLead Corporation
  • Low Porosity Pressureless Sintering of Novel Nano-Ag Paste For Die Attach
    Ning-Cheng Lee, Ph.D., Sihai Chen, Guangyu Fan, Xue Yan and Lee Kresge, Indium Corporation



    ET4

    Evolving Technologies Panel: Covering Key Technologies Including: Embedded Actives/Passives, 3D/TSV, Printed Electronics, Advanced Packaging Trends, EMS Trends, and Lead-Free Status

    FREE BEER AND PRETZELS!
    Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Lab
    Co-Chair: Paul Wang, Ph.D., Mitac International
    Monday, September 29 | 3:30pm - 5:00pm | Room 48

    Panelists include:
  • Lars Böttcher, Fraunhofer IZM Berlin
  • Steve Greathouse, Plexus Corp.
  • Happy Holden, Gentex Corporation (Retired)
  • Irene Sterian, P.E., Celestica, Inc.
  • E. Jan Vardaman, TechSearch International
  • Paul Vianco, Ph.D., Sandia National Labs
  • Chuck Woychik, Ph.D., Invensas








  • Harsh Environments Symposium
    FREE with a VIP or Technical Conference Registration!
    Organized by John Evans, Ph.D., and Pradeep Lall, Ph.D., Auburn University; Robert Kinyanjui, Ph.D., John Deere Electronic Solutions
    Monday, September 29 | 8:30am - 5:00pm | Room 45
    (Note: this symposium continues on Tuesday)


    HE1

    Harsh Environment Challenges with Lead-Free Solder

    Chair: John Evans, Ph.D., Auburn University
    Co-Chair: Dock Brown, DfR Solutions
    Monday, September 29 | 8:30am - 10:00am
    Room 45

    This session investigates the issues concerning the insertion of lead free solder materials in harsh environment applications. This includes alternatives to SAC305 solder materials.

  • Component Level Reliability for High Temperature Power Computing with SAC305 and Alternative High Reliability Solders
    Sivasubramanian Thirugnanasambandam, Ph.D., Auburn University
  • Can Sintered Silvers be Used in Surface Mount Applications
    Speaker of DistinctionChris Hunt, Ph.D., National Physical Laboratory
  • Measurement of the High Strain Rate Mechanical Behavior of SAC305 Alloy at Product Operating Temperature and Derivation of Anand Viscoplasticity Constants
    Speaker of DistinctionPradeep Lall, Ph.D., Di Zhang and Vikas Yadav, Auburn University; David Locker, US Army RDECOM



    HE2

    Thermal Solutions for Power Electronics

    Chair: Pradeep Lall, Ph.D., Auburn University
    Co-Chair: Marie Cole, IBM Corporation
    Monday, September 29 | 10:30am - 12:00pm
    Room 45

    Power electronics has found wide applications in automotive electronics. Electronic systems in automotive applications may be subjected to high temperatures over extended periods of time. In this session, thermal management, interconnect, and component deployment solutions for sustained reliable operation in automotive environments will be discussed. The first paper deals with the safety and manufacturing requirements related to the deployment of surface mount components in automotive applications. The second paper deals with the use of die attach materials for thermal management of high power modules. The third and fourth papers deal with interconnects for high temperature applications.

  • Die Attach Material as a Solution to Improve Thermal Performance of High Power Modules
    Mohammed Mansi, Bruce Fried, Ross Havens, Daryl Santos, Krishnaswami Srihari and Julia Zhao, Binghamton University
  • High Temperature Interconnects for Power Electronics
    Speaker of DistinctionHans-Juergen Albrecht, Ph.D., Siemens AG
  • New Interconnection for High Temperature Application: HotPowCon (HPC)
    Joerg Trodler, Heraeus Materials Technology GmbH & Co. KG and A. Fix, Robert Bosch and M. Nowottnick, University of Rostock



    HE3

    Reliability of Pb-Free Electronics in Harsh Environments

    Chair: Robert Kinyanjui, Ph.D., John Deere Electronic Solutions
    Co-Chair: Raiyo Aspandiar, Ph.D., Intel Corporation
    Monday, September 29 | 1:30pm - 3:00pm
    Room 45

    The first paper opens this session by looking at the effect of silver composition on high strain-rate fracture of Pb-free Tin-Silver-Copper (SAC) solder joints. The paper next discusses the critical strain energy release rate for crack initiation for SAC305, SAC0807 and SAC0307 Pb-free solder joints. The second paper presents results of accelerated thermal cycle tests (-55°C/125°C) of Pb-free DDR3 SDRAMs (in BGA packaging format), with and without high-Tg underfill materials. The third and fourth papers conclude the session by presenting modeling results of board-level life prediction based on product design, accelerated thermal cycling and materials aspects.

  • Effect of Solder Alloy, Aging and TAL on High Strain-Rate Fracture of Lead-Free Solder Joints
    Amir Nourani and Jan K. Spelt, University of Toronto
  • Impact of Solder Interconnect Geometry Modeling on Reliability Assessment Results of Electronic Assemblies
    Jingsong Xie, Ph.D., RelEng Technologies, Inc.
  • Temperature Cycling in Electronics
    Speaker of DistinctionCheryl Tulkoff and Tom O'Connor, DfR Solutions



    HE4

    Protecting Your Electronics Under Harsh Environment Conditions

    Chair: Scott Priore, Cisco Systems, Inc.
    Co-Chair: Rod Howell, Libra Industries
    Monday, September 29 | 3:30pm - 5:00pm
    Room 45

    These papers will look at several harsh conditions and propose ways in mitigating the effects they have on your electronics. From using Anti Sulfuric Resistor (ASR) to BGA protection, you will see what others have done to understand and reduce the environment's impact.

  • Mitigation of Resistor Silver Sulfide Corrosion Through Design and SMT Process Optimization
    Speaker of DistinctionMarie Cole, Biao Cai and Jing Zhang, IBM Corporation; Bae Byung Kwon, Jang In Seok, Ryu Jang Hwan and DongChul Gack, SK Hynix
  • Silver Sulfidation Kinetics in Flowers of Sulfur Environment
    Barry Hindin, Battelle and Michah Pledger, HzO, Inc.
  • Hydrophobic Coatings as an Approach for Preventing Corrosion Under BGAs
    J.D. Clifton, P.A. Panackal and K.F. Schoch Jr., Northrop Grumman Electronic Systems



    TUESDAY

    HE5

    Reliability and Qualification Considerations for Today's High Performance Electronic Assemblies

    Chair: Scott Nelson, Harris Corporation
    Co-Chair: Polina Snugovsky, Ph.D., Celestica, Inc.
    Tuesday, September 30 | 11:00am - 12:30pm
    Room 45

    Lead-free solder, wire-bondable substrate finishes, area array components, component miniaturization, and high density assembly are just a few of today’s material and process concerns facing the high performance electronics assembly industry. Proper qualification and implementation of these technologies is crucial to their insertion into high performance electronics used in modern automotive, medical, military, avionics, and space applications.

  • Effect of Gold and Copper on AuSn4 Redeposition and Isothermal Durability of SAC305 Solder Joints
    Subhasis Mukherjee and Abhijit Dasgupta, University of Maryland College Park; Julie Silk, Agilent Technologies and Lay-ling Ong, Agilent Technologies Malaysia
  • Assessment of the Effect of Mean Temperature on Thermal Cycling Reliability of SAC Solder Joints Using Leading Indicators of Failure
    Speaker of DistinctionPradeep Lall, Ph.D. and Kazi Mirza, Auburn University
  • Flip Chip Component Technology Qualification for High Performance Avionics Products
    Speaker of DistinctionDavid Hillman, Ross Wilcoxon, Lauren Schlueter and Ryan Walker, Rockwell Collins; Mario Scalzo and Dela Lara, Indium Corporation







    TUESDAY, September 30
    11:00am - 1:00pm


    AAT1

    Challenges and Advancements In 2.5D/3D Packaging

    Chair: Brian Roggeman, Qualcomm Inc.

    Co-Chair: Charles Bauer, Ph.D., TechLead Corporation
    Tuesday, September 30 | 11:00am - 1:00pm
    Room 44

    Continued advancements towards 3D packaging include interposer technology, ultra fine pitch features and through-silicon vias. Challenges in the implementation of these technologies, including detailed analysis of yield and reliability, will be presented.

  • 3DIC Yield Analysis Challenges
    Jacob Orbon, Rudolph Technologies
  • Scalable 3D IC Assembly Methods
    Charles G. Woychik, Ph.D., Sitaram Arkalgud, Ellis Chau, Andrew Cao, Liang Wang, Guilian Gao and Hong Shen, Invensas Corporation
  • 3D IC Integration with a TSV/RDL Passive Interposer
    John Lau, Ph.D., ASM Pacific Technology
  • A Novel Organic Interposer with Ultra Fine Interconnect for 2.5D Packaging
    Christian Romero, P.E., Youngdo Kweon, Mijin Park and Jeongho Lee, Samsung Electromechanics Co.



    MFX1

    Overcome the Challenges of Liquid Soldering Processes

    Chair: Ursula Marquez de Tino, Ph.D., Plexus Corp.
    Co-Chair: Keith Howell, Nihon Superior
    Tuesday, September 30 | 11:00am - 12:30pm
    Room 49

    Thermally challenging assemblies are pushing the limits of liquid soldering processes such as wave and selective soldering. Boards require increased soldering temperatures in order to obtain acceptable joints. This requirement results in copper dissolution. How far can we push the process without causing reliability issues? Another concern is flux spreading; flux that ends up in areas that do not see enough heat. These are risk areas for electro-migration. What are the factors that minimize the spreading?

  • Copper Dissolution as a Function of Surface Finish as Observed on RoHS Selective Solder Equipment
    *Thomas Shoaf, Plexus Corp.
  • Sensitivity of Copper Dissolution to the Flow Behavior of Molten Sn-Pb Solder
    *Paul Vianco, Ph.D., J.A. Rejent, A.C. Kilgo and S.E. Garrett, Sandia National Laboratories
  • Reliable Soldering for High and Mixed Volume Selective Soldering Processes
    Gerjan Diepstraten, Vitronics Soltec BV



    TUESDAY, September 30
    2:00pm - 3:30pm


    AAT2

    Chip Scale Package Reliability

    Chair: Andrew Mawer, Freescale Semiconductor
    Co-Chair: S. Manian Ramkumar, Ph.D., Rochester Institute of Technology
    Tuesday, September 30 | 2:00pm - 3:30pm
    Room 44

    With the increased use in the industry of Chip Scale Packages (CSP) at 0.3 to 0.5 mm and even finer pitches comes increased scrutiny on various aspects of their assembly and reliability. Specifically, there are challenges to the assembly process at these fine pitches as well as concerns regarding the reliability of the CSP solder joints under thermal cycling, drop/shock as well as high current. This session will explore various topics related to the SMT assembly, including underfilling, inspection, accelerated testing, reliability and failure analysis of CSPs, including Wafer Level CSPs.

  • Electromigration Performance of WLCSP Solder Joints
    *Robert Darveaux, Ph.D., Jimmy-Ding V Hoang and Vijay Vijayakumar, Skyworks Solutions, Inc.
  • Assembly and Failure Analysis of WLP With Pitch Less Than or Equal to 0.3mm
    *Dudi Amir and Chonglun Fan, Intel Corporation
  • Reworkable Underfill Evaluation for Fine Pitch CSP Applications
    Fei Xie, Ph.D., Han Wu, Daniel F. Baldwin, Ph.D., and Paul N., Engent



    MFX2

    Organic Compatibility in Assembly: Effect on Electrical Performance

    Chair: Martin Anselm, Ph.D., Universal Instruments Corporation
    Co-Chair: Brian Roggemann, Qualcomm
    Tuesday, September 30 | 2:00pm - 3:30pm
    Room 49

    Organic compounds are abundant in electronics manufacturing. Their reactions and interactions can significantly affect quality assessment testing methodologies. This session identifies some of the typical interaction mechanisms and how these interactions impact electro-chemical testing methodologies. This topic becomes especially poignant in the context of miniaturization.

  • Assembly Material/Flux Interactions and the Impact on Reliability
    *Ian Wilding, Gavin Jackson, Katherine Day, Richard Boyle, Michael Carter and Daniel Buckland, Henkel Ltd.
  • Effect of Flux Systems on Electrochemical Migration of Lead-Free Assembly
    Xiang Wei, Ph.D., Kester ITW
  • The Effect of Solder Paste Reflow Conditions on Surface Insulation Resistance
    Karen Tellefsen, Ph.D. and Mitch Holtzer, Alpha



    SMT1

    BTC Best Practices

    Chair: Chrys Shea, Shea Engineering Services
    Co-Chair: Ray Whittier, Vicor Corporation
    Tuesday, September 30 | 2:00pm - 3:30pm
    Room 47

    Bottom Termination Components (BTCs) are going mainstream. The relatively low cost and good reliability associated with QFNs, DFNs, MLFs and LGAs make them a popular choice for semiconductor manufacturers, but they bring with them a host of new concerns for designers and manufacturers. This session focuses on best practices, with an overview of typical considerations in design and manufacturing, proven DFM principles, and an evaluation of economical, process-friendly thermal via design.

  • BTC: Bottom Termination Component or Biggest Technical Challenge?
    *Cheryl Tulkoff and Greg Caswelll, DfR Solutions
  • BTCs: Packages We Love to Hate
    *Dale Lee, Plexus Corp.
  • Via-in-Pad Design Considerations for Bottom Terminated Components on Printed Circuit Board Assemblies
    *Matt Kelly, P.Eng, MBA, Mark Jeanson and Mitch Ferrill, IBM Corporation



    PRC1

    Radiography Techniques for Inspection of Advanced Electronic Packages

    Chair: Bill Cardoso, Ph.D., Creative Electron
    Co-Chair: Shean Dalton, PricoTex
    Tuesday, September 30 | 2:00pm - 3:30pm
    Room 51

    Recent advances in electronic packaging technologies challenge quality inspection efforts of PCBA manufacturing processes. The impact of interfacial voiding using x-ray systems and bondtester reliability in BGAs is presented. The adoption of package-on-package devices has increased, and with that the difficulty in optimizing radiography techniques for quality assurance. Further studies in computer tomography for the non-destructive evaluation in high-end electronic packages are shown to greatly improve the overall quality control process in PCBA manufacturing and electronic packaging.

  • X-ray / Bondtester Reliability Study of BGA Devices – Impact of Interfacial Voiding
    *Evstatin Krastev, Ph.D., Nordson DAGE
  • Optimizing X-Ray Inspection With Package on Package
    Zhen (Jane) Feng, Ph.D., David Geiger, Weifeng Liu, Ph.D., Hung Le, Tho Vu, Anwar Mohammed and Murad Kurwa, Flextronics International; Evstatin Krastev, Ph.D., Nordson DAGE
  • X-Ray Micro-CT for Non-destructive Analysis of Cracks and Defects in Fine-Pitch Electronic Packages
    *Pradeep Lall, Ph.D., Shantanu Deshpande and Junchao Wei, Auburn University



    TUESDAY, September 30
    4:00pm - 5:30pm


    AAT3

    Ceramic Column Grid Array-Optimization and Evaluation

    Chair: Marie Cole, IBM Corporation
    Co-Chair: Richard Coyle, Ph.D., Alcatel-Lucent
    Tuesday, September 30 | 4:00pm - 5:30pm
    Room 44

    Ceramic Column Grid Array packages are a good alternative to BGA packages for high I/O, high performance and/or high reliability applications. Learn how to use CCGAs successfully in these applications. This session will share best practices for optimizing CCGA design and assembly processes. It will also include the results from thermo-mechanical solder joint reliability evaluations of both components incorporated into the package assembly and the assembled CCGAs.

  • Ceramic Column Grid Array Design and Assembly
    *Scott Nelson, Harris Corporation
  • Reliability of Capacitors/CGAs Onto Substrate/PCB
    Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
  • Comparative Analysis of cCGA Solder Column Interconnects Following Aerospace Level Vibration Testing to Failure
    Jeff Jennings, Harris Corporation



    MFX3

    Polymeric Assembly Materials

    Chair: Richard Kraszewski, Plexus Corp.
    Co-Chair: Jeff Sargent, Chase-Humiseal
    Tuesday, September 30 | 4:00pm - 5:30pm
    Room 49

    Polymeric assembly materials are an integral part of the long term reliability of electronic products. This session provides detail as to the proper application and rework of some of those critical materials.

  • Conformal Coating Over No Clean Flux, Part 2
    Timothy O'Neill and Karl Seelig, AIM
  • Component Removal Techniques With Underfill on Printed Circuit Boards for Failure Analysis
    Priyanka Dobriyal, Ph.D., Anil Kurella and James Wade, Intel Corporation
  • Development of an Underfill Rework Process
    Jenny England, Ph.D., Brian J. Toleno, Ph.D. and Jonathan Israel, Henkel Electronic Materials, LLC



    SMT2

    Minimizing Voids Under QFNs, BGAs and Discrete Components

    Chair: Bob Farrell, Benchmark Electronics, Inc.
    Co-Chair: Mike Nadreau, Henkel Electronic Materials
    Tuesday, September 30 | 4:00pm - 5:30pm
    Room 47

    Voids occur under QFNs due to their low standoff which makes it difficult for flux volatiles to escape during reflow. This session presents various techniques to minimize QFN voids via Design for Manufacturing (DFM) improvements on the printed circuit board, the use of solder preforms, and stencil aperture design. Profile modifications designed to mitigate voiding on all components including QFNs, BGAs, and discrete components are discussed.

  • QFN Design Considerations to Improve Cleaning – A Follow on Study
    *Mike Bixenman, D.B.A., Kyzen Corporation; Dale Lee, Plexus; Bill Vuono, TriQuint Semiconductor; Steve Stach, AAT
  • Advancement of Preform Technology to Reduce QFN Voiding
    *Tim Jensen, Indium Corporation
  • Eliminating BTC Voiding on the Fly: In-Production Optimization Techniques Part II
    *Rafael Padilla, P.E., Satoru Akita, Derek Daily, Tokuro Yamaki, Hideki Mori, Tomoyasu Yoshikawa and Masato Shimamura, Senju Comtek Corporation; Kazuyori Takagi and Ko Inaba, Senju Metal Industry Co., Ltd.



    PRC2

    Advances in Production Inspection Methods

    Chair: States Mead, The Morey Corporation
    Co-Chair: Mumtaz Bora, Peregrine Semiconductor
    Tuesday, September 30 | 4:00pm - 5:30pm
    Room 51

    The growing complexity of today's electronics manufacturing is requiring inspection technologies to provide timely feedback and accurate information to the manufacturing engineers for guidance in process improvement efforts. As users gain experience with inspection technologies, they are devising new and innovative ways to improve the usefulness and robustness of inspection at every step of the process. This session will cover unique advanced techniques without the need for CAD data, near-to-zero setups and importance in true height measurements, and DOE benefits comparing stencil coatings.

  • Complicated Board Programming for Automated Printed Solder Paste Inspection without CAD Data File
    Run-Sheng Mao, Ph.D. and Ning-Cheng Lee, Ph.D., Indium Corporation
  • Inspection Strategies for More Accurate, Faster and Smarter Inspection
    Brendan Hinnenkamp, CyberOptics Corporation
  • Highly Accurate 3D Solder Paste Inspection Comparing Nano Coated Stencils With Non-Coated Results
    Carsten Salewski and Jacques L'Heureux, Viscom Inc.



    WEDNESDAY, October 1
    8:00am - 10:00am


    AAT4

    Next Generation of Package-on-Package (PoP) Challenges

    Chair: Chuck Woychik, Ph.D., Invensas Corporation
    Co-Chair: Lars Böttcher, Fraunhofer IZM Berlin
    Wednesday, October 1 | 8:00am - 9:30am
    Room 44

    Package-on-Package (PoP) is the benchmark platform for assembling the processor and memory packages for mobile products. In this session, results of a study on reliability testing of different Pb-free solder alloy combinations and technical challenges for optimizing materials and processes to manufacture a large 50mm x 50mm PoP module will be presented. A new high performance PoP technology called Bond-Via-Array (BVA) has been developed that enables over 1000 interconnects on a standard outline that is ready for HVM.

  • Influence of Thermal Shock on Alloy Combinations in Package on Package Assemblies
    *S. Manian Ramkumar, Ph.D. and Andrew Daya, Rochester Institute of Technology
  • Package on Package Module Assembly Process Development
    Scott Priore and Chuan Xia, Cisco Systems, Inc.
  • Manufacturing Readiness of BVA™ Technology for Fine-Pitch Package-on-Package
    Wael Zohni, Rajesh Katkar, Rey Co and Rizza Cizek, Invensas



    MFX4

    Solder and Cleaning Process Selection and Control

    Chair: Linda Woody, Lockheed Martin
    Co-Chair: Jack Reinke, Kyzen Corporation
    Wednesday, October 1 | 8:00am - 10:00am
    Room 49

    Today's electronics are increasingly more complex and as the density of electronic circuit cards increases soldering and cleaning also becomes more complex. This session will explore the methodologies for developing soldering and cleaning processes. Process control will be discussed and detailed test protocols will be reported. Impacts to circuit card assembly reliability will be explored as a direct consequence of soldering and cleaning process selection.

  • The Effect of Thermal Profiles on Cleanliness and Solder Joint Quality
    *Eric Camden, Foresite
  • Cleaning Process Efficiency and the Influence of Static & Dynamic Cleaning Rates
    *Umut Tosun, M.S. Ch.E., Kalyan Nukala, M.S. Ch.E., Axel Vargas and Thien Vu, ZESTRON America
  • Real Time Monitoring of the Aqueous Cleaning Wash Bath
    Ram Wissel, David Lober, Dirk Ellis and Mike Bixenman, Kyzen Corporation
  • To Kill a Circuit Board: Perils in Manual Soldering & Cleaning Processes
    *Cheryl Tulkoff, DfR Solutions



    SMT3

    PCB Component/Connector Rework-From Small to Large

    Chair: Glen Thomas, Indium Corporation
    Co-Chair: Laura Turbini, Ph.D., Independent Reliability Consultant
    Wednesday, October 1 | 8:00am - 9:30am
    Room 47

    Component rework of Printed Circuit Boards is a crucial part of any production process. Without a viable rework process, your early hardware deliveries will likely not be on schedule and your production yields and costs will not meet your objectives. This session shares recent work done to rework components (large and small) as well as connectors.

  • Methods for 01005 Component Rework
    Bob Wetterman and Hung Hoang, BEST Inc.
  • Removal of High Density Plated Through Hole Connectors on Large Mass Multi-Layered Circuit Card Assemblies
    Michael Newman, Harris Corporation
  • Rework of High Thermal Mass BGAs, QFNs, and SMT Connectors on Pb-free Circuit Board Assemblies with Temperature Sensitive Optical Fiber
    Robert Farrell, Benchmark Electronics; Jeff Duhaime, Air-Vac Engineering



    SUB1

    Solderable Final Finishes

    Chair: Don Banks, St. Jude Medical
    Co-Chair: Rob Rowland, Axiom Electronics
    Wednesday, October 1 | 8:00am - 9:30am
    Room 45

    PCB assembly presents challenges for solderable final finishes. Options available include OSP and ENIG. Each will be discussed along with equipment and process parameters that can influence performance. The immersion Sn process has inherent corrosion resistance. It has gained market share and continues to evolve. Cu roughness can affect surface finish plating. Microetch chemistry reduces the real surface area roughness and may enhance the performance characteristics of the final finish.

  • Critical Process and Chemical Parameters Affecting the Assembly Performance of Organic Solderability Preservatives (OSP)
    *Michael Carano, OM Group Electronic Chemicals, LLC
  • Immersion Tin Surface Finish – Reviewing the Past and a Look to the Future
    Mustafa Oezkoek, Ph.D., P.E., Hubertus Mertens, Gustavo Ramos and Maren Bruder, Atotech
  • Controlling High Copper Roughness for Increased Surface Finish Performance
    *Lenora Toscano, Aaron Karoly and Ernest Long, Ph.D., MacDermid



    WEDNESDAY, October 1
    10:30am - 12:30pm


    AAT5

    BGA Solder Joint Reliability

    Chair: Randy Schueller, Ph.D., DfR Solutions
    Co-Chair: Pradeep Lall, Ph.D., Auburn University
    Wednesday, October 1 | 10:30am - 12:30pm
    Room 44

    Solder joints on ball grid array packages wear out and fail due to growth of fatigue cracks. With each new investigation we gain a better understanding of how variables such as pad size, die size/thickness, package size/thickness, solder alloy, pre-aging, etc., impact the failure rate of the solder joints. These four papers reveal important new findings that attendees can use to improve the life of their BGA packages.

  • Design and Material Parameter Effects on BGA Solder Joint Reliability for Automotive Applications
    Burton Carpenter, Thomas Koschmieder, Brett Wilkerson, John Arthur and Torsten Hauck, Freescale Semiconductor
  • Effect of Board Thickness, Temperature Range, and Dwell Time on Solder Joint Reliability of FCBGA Packages Based on IPC9701 Characterization
    Jagadeesh Radhakrishnan, Olivia H. Chen, Al Molina and Russ Brown, Intel Corporation
  • Effect of Isothermal Preconditioning on Thermal Fatigue Life and Microstructure of a SAC305 BGA
    Jim Wilcox, Ph.D., IEEE HDP User Group, International; Richard Coyle and Joe Smetana, Alcatel Lucent; Lawrence Lehman, Binghamton University
  • Reliability Evaluation of Ultra Large BGA System-in-Package (SiP) Module Assemblies
    Weidong Xie, Ph.D., Cherif Guirguis, Qiang (Johnson) Wang and Mudasir Admad, Cisco Systems, Inc.



    MFX5

    Adhesive Applications

    Chair: Richard Henrick, Sanmina Corporation
    Co-Chair: Iulia Muntele, Ph.D., Sanmina Corporation
    Wednesday, October 1 | 10:30am - 12:00pm
    Room 49

    From surface mount adhesives to conformal coatings, to underfills, adhesives have long been used in electronics manufacturing. In some cases they enable certain processes and in some cases they are used to improve reliability. In this session we will discuss new ways of applying and curing these adhesives as well as some new adhesive applications.

  • Advanced Micro-Dispensing of High Viscosity Adhesives and Polymers
    Xudong Chen, Jacob Denkins and Kenneth H. Church, nScrypt Inc.
  • An Innovative Reliability Solution to Interconnect of Flexible/Rigid Substrates
    Wusheng Yin, Ph.D. and Mary Liu, YINCAE Advanced Materials, LLC
  • Encapsultant Materials Designed for Increasing Reliability and Protection of Electronic Devices
    Brian J. Toleno, Ph.D. and Jan Wijaerts, Henkel Electronic Materials



    SMT4

    Stencil Printing Advances for Today's Electronics

    Chair: Ray Whittier Jr., Vicor Corporation
    Co-Chair: William Coleman, Ph.D., PhotoStencil
    Wednesday, October 1 | 10:30am - 12:00pm
    Room 47

    Electronic device miniaturization continuously challenges solder paste stencil printing technology, driving research and development on methods of printing smaller, denser deposits with robust, high-yielding processes. This session highlights recent advances in materials, equipment and characterization methods for fine feature solder paste printing. Data will be presented on solvent underwiping, nanocoating, process controls, and other technological advances that enable the quest to build smaller, more powerful electronics.

  • Performance Enhancing Nano Coatings: Changing the Rules of Stencil Design
    *Tony Lentz, M.B.S., FCT Assembly
  • Advances in Fine Pitch Printing Process Technology
    Michael Martel and Isaiah Smith, Speedline Technologies Inc.
  • Understencil Video Effects to Study Solder Paste Transfer and Wiping Effects
    *Mike Bixenman, D.B.A. Kyzen Corporation; Chrys Shea, Shea Engineering Services; Brook Sandy, Indium Corporation; Ray Whittier, Vicor Corporation



    SUB2

    PCB Technology: Assembly Challenges and Defects Resulting from PCB Design

    Chair: Lenora Toscano, MacDermid
    Co-Chair: Barry Hindin, Battelle
    Wednesday, October 1 | 10:30am - 12:00pm
    Room 45

    As the landscape of PCB designs change, new challenges arise in manufacture and assembly. Strong focus has been placed on how these designs will affect manufacture but there are significant challenges experienced during and after assembly which must also be resolved. This session discusses new materials and assembly techniques to some industry issues. It also reviews a new defect experienced during assembly which result from recent design changes.

  • Thick Copper Printed Circuit Board Assembly Technology and Process Development
    Richard Loi, Ph.D., Dennis Willie, David Geiger and Murad Kurwa, Flextronics
  • Spherical Bend Test Failure Criteria Correlation in Compliant Systems
    *John McMahon, P.E., Brian Standing and Meisam Salahi, Celestica, Inc.
  • Electroless Nickel Immersion Gold and Black Tar. What Is It and How Can It Be Prevented?
    James Trainor, OM Group Electronic Chemicals, LLC



    WEDNESDAY, October 1
    2:00pm - 3:30pm


    AAT6

    Failure Analysis and Characterization Methods

    Chair: Burt Carpenter, Freescale Semiconductor
    Co-Chair: Denis Barbini, Ph.D., Universal Instruments
    Wednesday, October 1 | 2:00pm - 3:30pm
    Room 44

    Physical and chemical analysis of packaging and interconnects is required for characterization of components and processes, inspection during and after manufacturing, and failure analysis in the event of qualification or field failures. This session examines a variety of analysis techniques including visual, X-ray, mechanical sectioning, SEM, Ion Chromatography, and Laser Ultrasonic Inspection (LUI), applied to study solder interconnects and surface mount components.

  • Characterization and Failure Analysis Techniques for Ball Grid Array Solder Joints
    Adam W. Mortensen, Maria C. Lee and Roger M. Devaney, Hi-Rel Laboratories
  • Root Cause Failure Analysis Test Comparisons
    Terry Munson, Foresite
  • Non-Destructive Evaluation of Solder Bump Quality Under Mechanical Bending Using Laser Ultrasonic Technique
    Jie Gong and Charles Ume, Georgia Institute of Technology; Kola Akinade, Ph.D., Bryan Rogers, Cherif Guirguis, David Chan and Mark Hill, Cisco Systems, Inc.



    MFX6

    Alternate Alloys

    Chair: Jean-Paul Clech, Ph.D., EPSI, Inc.
    Co-Chair: Kola Akinade, Ph.D., Cisco Systems
    Wednesday, October 1 | 2:00pm - 3:30pm
    Room 49

    The need for varied levels of board assembly reliability continues to drive solder alloy development and materials characterization. Materials and soldering experts will present avenues that are being pursued to improve lead-free processes and board level reliability: new paste materials that allow local control of soldering temperatures, addition of trace metals to improve the impact resistance of lead-free solders, and enhanced measurement techniques for rapid characterization of solder joint properties.

  • Soldering with Exothermic Reacting Pastes
    Mathias Nowottnick, Dirk Seehase and Heiko Huth, University of Rostock
  • Enhancing the Impact Properties of Tin-Copper and Tin-Copper-Nickel Lead-Free Solders with Trace Additions of Zinc, Indium and Gold
    *Keith Sweatman and Takatoshi Nishimura, Nihon Superior Co., Ltd.; Dekui Mu, University of Queensland
  • Mapping Mechanical Properties of Lead-Free Solder Joints
    Carlos Morillo, University of Maryland CALCE; Julie Silk, Agilent Technologies



    SMT5

    Tools for Sustainable Stencil Printing

    Chair: Jeff Schake, DEK USA
    Co-Chair: Jason Hall, TS3 Technology, Inc.
    Wednesday, October 1 | 2:00pm - 3:30pm
    Room 47

    The stencil printing process has historically adapted to shrinking component technology requirements by using thinner stencils in order to maintain aperture area ratio levels that ensure satisfactory paste transfer. However, sustainability of future stencil printing success will require new engineering innovations beyond this strategy alone. Join us for informative reporting of formal printing research highlighting equipment and stencil technology developments, along with a production validated comprehensive stencil supplier study.

  • The Next Big Challenge for Stencil Printing - Sub 0.5 Area Ratio Apertures
    *Mark Whitmore and Clive Ashmore, DEK Printing Machines Ltd.
  • Fundamental Study on a Secure Printing Process Using NanoWork Stencils for 01005 Components
    Stefan Haerter and Joerg Franke, University of Erlangen-Nuremberg; Carmina Laentzsch, LaserJob GmbH
  • The Effects of Stencil Alloy, Tension and Cut Quality on Solder Paste Print Performance
    *Chrys Shea, Shea Engineering Services and Ray Whittier, Vicor Corporation



    SUB3

    New PCB Finishes

    Chair: Raiyo Aspandiar, Ph.D., Intel Corporation
    Co-Chair: Robert Kinyanjui, Ph.D., John Deere Electronic Solutions
    Wednesday, October 1 | 2:00pm - 3:30pm
    Room 45

    In the drive for improving performance of PCB surface finishes, preferably at a reduced manufacturing cost, new surface finishes are being constantly developed and evaluated within the electronics manufacturing industry. This session will describe three such efforts on the development of new surface finishes and their performance during soldering and post soldering assembly operations for PCBs.

  • Comparative Study of Next-Generation Surface Finishes for Printed Circuit Assembly
    Sue Teng and Scott Priore, Cisco Systems, Inc.
  • Soldering Evaluations on the New Direct Palladium Gold Finish (EPAG)
    Mustafa Oezkoek, Ph.D., P.E., Arnd Kilian, Gustavo Ramos, Maren Bruder and Petra Schreier, Atotech
  • Improving Electronics Assembly Process Through Organic-Metal Final Finish
    *Rita Mohanty, Ph.D., John Fudala and Sathiya Nararana, Enthone



    EMS1

    Supply Chain Conflict Minerals Compliance

    Chair: Susan Mucha, Powell-Mucha Consulting, Inc.
    Co-Chair: Mike Buetow, UP Media Group
    Wednesday, October 1 | 2:00pm - 3:30pm
    Room 51

    In the wake of the Dodd-Frank legislation mandating reporting of minerals mined in war-torn regions like the DRC, several initiatives and templates for defining and reporting use of these elements have been developed by worldwide organizations, including the Conflict-Free Tin Initiative, the EICC Conflict-Free Smelter Program, and the IPC Conflict Minerals Due Diligence Guide. This session looks at where these programs intersect, best practices for compliance, and some of the tools for compliance.

  • Contract Manufacturing and Conflict Minerals: Creating a Workable Compliance System
    John Sheehan, SigmaTron International
  • Lessons Learned from AIM's Participation in the CFTI
    David Suraski, AIM
  • Panel Discussion
    Aidan Turnbull, Ph.D., ENVIRON International; Chris Nowak, Actio



    WEDNESDAY, October 1
    4:00pm - 5:30pm


    AAT7

    Low Temperature Assembly, Fluxes and Standards

    Chair: Eric Bastow, Indium Corporation
    Co-Chair: Mike Bixenman, DBA, Kyzen Corporation
    Wednesday, October 1 | 4:00pm - 5:30pm
    Room 44

    The first paper in this session will discuss low temperature LED assembly on flexible substrates. The second paper will present the effect of NaCL contamination on Sn metallization coating Alloy 42 component leads. A variety of stressing environments and tests procedures were performed to determine the effect of the NaCl exposure. The session will finish with a summary paper discussing some of the new and perhaps confusing aspects of IPC J-STD-004.

  • Low Temperature Assembly of LED Packages on PET & Polyimide Substrates
    Amit Patel, Alpha-Energy Technologies
  • Several Studies of NaCl Presence on Tin Metallization
    Jose Servin, Continental Automotive Guadalajara
  • J-STD-004B: A New Twist on an Old Standard?
    Karl Seelig and Tim O'Neill, AIM



    MFX7

    Lead-Free Alloys End Use-Application Reliability

    Chair: Dale Lee, Plexus Corp.
    Co-Chair: Tim Jensen, Indium Corporation
    Wednesday, October 1 | 4:00pm - 5:30pm
    Room 49

    Lead free solder alloys have been studied and used in electronic assemblies for several years now. However, the alloy continues to evolve with use of low silver alloys, grain modifier alloys and low melting point alloys. Reliability information continues to develop for these alloys and their effects when mixed with other alloys in production. This session will look at effects of using these alloys on intermetallic compound formation and reliability impacts.

  • Microstructure Study of Lead-Free Solder Joints Assembled Using Alternative Low Silver Alloy Solder Pastes
    Elissa McKay, Flextronics
  • Reliability of PCB Solder Joints Assembled with SACM Solder Paste
    *Ning-Cheng Lee, Ph.D., Arnab Dasgupta, Fengying Zhou, Weiping Liu, Paul Bachorik and Christine LaBarbera, Indium Corporation
  • Low-Temperature Soldering of Si-based Photo Multipliers
    Mo Biglari, Ph.D., Marjolijn Menninga, Roel Denteneer, Ludo Krassenburg and Erik Brom, Mat-Tech BV



    SMT6

    Extreme SMT Challenges and Questions

    Chair: Tom Borkes, The Jefferson Project
    Co-Chair: Xiang (Shawn) Wei, Kester
    Wednesday, October 1 | 4:00pm - 5:30pm
    Room 47

    To produce the most cost effective and reliable electronic products, our task is to maximize yield, minimize rework and select the materials that will best serve the products over their lifetimes. We do this by trying to minimize process variability and maximize the process window. In addition we need to understand the metallographic consequences of the solder that we use. This session presents three leading edge papers that address these objectives in areas of extreme solder process difficulty and concern. And while they are largely a function of the immutable laws of physics (such as the thermal coefficient of expansion and grain structure), these papers provide valuable insight and data that help us cope with these issues.

  • Microstructure and Reliability Studies of Mixed SnPb and Pb-free BGA Soldering
    Ken Kramer, Ph.D., Alok Sharan and Corey Nelson, Micro Systems Engineering
  • A.R.E.A.-Component Warpage: Issues With Measurement and Standardization
    *Martin Anselm, Ph.D., Universal Instruments Corporation
  • Studies on PCB Warpage Due To The Interaction Between Large BGA Package and PCB with VIPPO or Back Drill Design
    Steven Perng, WeiDong Xie and David Chan, Cisco Systems, Inc.



    SUB4

    Impact of Surface Finishes on Reliability of Interconnects

    Chair: Srini Chada, Ph.D., Schlumberger
    Co-Chair: Joe Colangelo, Raytheon
    Wednesday, October 1 | 4:00pm - 5:30pm
    Room 45

    To form a solder joint or to mate a connector, surface finishes are essential as they supply the elements required for a chemical reaction to form a metallurgical bond or a durable surface for mechanical contact. In this session we explore the effect of several popularly used, as well as emerging surface finishes on the reliability of solder joints owing to their interactions with Pb-free solders during joint formation and in-field application. In addition, a method to optimize Au plating thickness used in mechanical connections under several use conditions is presented.

  • Thermal Aging and Cycling Effects on the Reliability of Sn-Ag-Cu Solder Joints With Various Materials Finished on the Board
    Chaobo Shen, Zhou Hai, Cong Zhao, Jiawei Zhang, MJ Bozack and John L. Evans, Ph.D., Auburn University
  • Connector Reliability: Tradeoff Between Surface Plating and Mechanical Solutions
    Karumbu Meyyappan, Anil Kurella, Alan Mcallister and Balu Pathangey, Intel Corporation
  • Pb Free Solder Joint Reliability of Various Surface Finishes
    Yoshinori Ejiri, Takehisa Sakurai, Yoshinori Arayama, Yoshiaki Tsubomatsu, Kunihiko Akai, Masashi Nakagawa and Kiyoshi Hasegawa, Hitachi Chemical Co., Ltd.



    THURSDAY, October 2


    Lead-Free Soldering Technology Symposium
    Organized by Paul Vianco, Ph.D., Sandia National Laboratories, and Matthew Kelly, P. Eng., MBA, IBM Corporation
    Thursday, October 2 | 8:00am - 5:00pm | Room 49

    Free with a VIP or Technical Conference Registration!


    LF1

    Material Evaluation for High Reliability Applications: A.R.E.A. Consortium

    Chair: Richard Coyle, Ph.D., Alcatel-Lucent
    Co-Chair: Matthew Kelly, P.Eng., MBA, IBM Corporation
    Thursday, October 2 | 8:00am - 9:30am
    Room 49

    This session provides attendees with a snapshot into some of the material selection options for high reliability RF and high speed product design. Material aspects such as laminate material, surface finish, and TIMs are evaluated. In this case, results from various accelerated tests are interpreted and discussed such as specific laminates are evaluated for cratering resistance, the impact of surface finishes on solder joint reliability are compared in thermal cycling reliability and microstructure, and TIM thermal resistance measurements were compared to data published by the manufacturer.

  • A.R.E.A. - Low Loss Laminate Material Pad Cratering Resistance Resistance
    Michael Meilunas and Martin Anselm, Ph.D., Universal Instruments Corporation
  • A.R.E.A. - Effect of PCB Surface Finish on Sn Grain Morphology and Thermal Fatigue Performance of SnPb and Lead Free Solder Joints
    Speaker of DistinctionBabak Arfaei, Ph.D., Francis Mutuku and Martin Anselm, Ph.D., Universal Instruments Corporation
  • A.R.E.A. - Component Level Testing of Thermal Interface Materials
    Harry Schoeller, Ph.D. and Martin Anselm, Ph.D., Universal Instruments Corporation



    LF2

    On-Going, Lead-Free Research, Development and Knowledge Sharing Priorities

    Chair: Matthew Kelly, P.Eng., MBA, IBM Corporation
    Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Thursday, October 2 | 10:00am - 11:30am
    Room 49

    Even with the significant progress made to date, there are still several key areas of R&D and knowledge sharing that remain as portions of the industry continue their transition to lead-free solder assembly. Several market segments continue to learn more about reliability implications and risk mitigation options for tin whiskers, temperature sensitive components, and assembly chemistry electro-migration. This session brings together these topics in three publications from the IPC PERM (Pb-free Electronics Risk Mitigation) Council, HDPug (High Density Packaging User Group), and leading research from an industry materials and solder manufacturer. Together, they encompass today's on-going lead-free R&D and knowledge sharing priorities.

  • Recalling the Lead-Free Manhattan Project: Pb-free Technology Knowledge Gaps Priorities
    Anthony Rafanelli, Ph.D., P.E., Raytheon Company and Linda Woody, Lockheed-Martin
  • Process Sensitive Components Guideline-a Primer for the Industry
    Speaker of DistinctionMarie Cole, Curtis Grosskopf, Michelle Lam, and Michael Lauri, IBM Corporation; David Geiger, Flextronics; Holly-Dee Rubin, Alcatel-Lucent; Thil Sack, Celestica; Mike Bixenman, Kyzen Corporation; Laurence Schultz and James Wilcox, HDPUG
  • "Smart" Chemistry Towards Highly Efficient Soldering Material Formulation
    Yanrong Shi, Ph.D. and Xiang Wei, Ph.D., Kester Inc.



    LF3

    Tin Whisker Research and Mitigation

    Chair: Jeff Kennedy, Celestica Inc.
    Co-Chair: Elizabeth Benedetto, Hewlett-Packard
    Thursday, October 2 | 12:30pm - 2:30pm
    Room 49

    Pb-Free challenges for high reliability products are driving research to explore solutions that will reduce the risk of tin whiskers causing short circuits. This session will give an overview of the problem and summaries of the current research being done to understand tin whisker formation and growth mechanisms as well as novel and unique conformal coating material developments to mitigate the risk that will contain or alter the surface growth mechanisms to lower the risk to an acceptable value.

  • Risk and Mitigation for Tin Pest and Tin Whiskers
    Speaker of DistinctionRonald Lasky, Ph.D., P.E., Indium Corporation
  • Tin Whisker Testing and Modeling
    Stephan Meschter, Ph.D., BAE Systems; P. Snugovsky, J. Kennedy, Z. Bagheri and E. Kosiba, Celestica, Inc.
  • Tin Whisker Inorganic Coating Evaluation (TWICE)
    Speaker of DistinctionDavid Hillman, Dan Grossman, Ross Wilcoxon and Nate Lower, Rockwell Collins
  • Nanoparticle Enhanced Conformal Coating for Whisker Mitigation
    Stephan Meschter, Ph.D., BAE Systems; Junghyun Cho and Suraj Maganty, Binghamton University; Dale Starkey, Mario Gomez and David Edwards, Henkel Electronic Materials; Abdullah Ekin and Kevin Elsken, Bayer Material Science; Jason Keeping, Polina Snugovsky, Ph.D. and Jeff Kennedy, Celestica



    LF4

    Lead-Free Solder Joint Reliability

    Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Co-Chair: Kola Akinade, Ph.D., Cisco Systems, Inc.
    Thursday, October 2 | 3:00pm - 5:00pm
    Room 49

    As Pb-free soldering makes further inroads into the high-reliability electronics community, solder joint reliability modeling is taking on many new and exciting pathways. The papers in this session include a re-examination the Norris-Landzberg model that had its beginnings in some of the earliest efforts to predict Sn-Pb fatigue. The second presentation describes the ability to adapt the constitutive model to the microstructural evolution of the solder as a means to improve the fidelity of the predictions. The last two papers summarize an important iNEMI test program that investigated, specifically, the effect of silver (Ag) content on the thermal mechanical fatigue and drop shock resistance of Sn-Ag-Cu solders.

  • A Closed-Form Norris-Landzberg Solder Reliability Model
    Emad Al-Momani, Ph.D., Intel Corporation
  • Microstructurally Adaptive Constitutive Relations and Reliability Assessment Protocols for Lead Free Solder
    Peter Borgesen, Ph.D. and E. Cotts, Binghamton University; I. Dutta, Washington State University
  • INEMI PB-Free Alloy Characterization Project Report: Part VII – Thermal Fatigue Results for High-AG Alloys at Extended Dwell Times
    Speaker of DistinctionRichard Coyle, Ph.D., Alcatel-Lucent; Richard Parker, Delphi; Keith Howell and Keith Sweatman, Nihon Superior Co. Ltd.; Aileen Allen and Elizabeth Benedetto, Hewlett-Packard Co., Stuart Longgood, Delphi and Joseph Smetana, Alcatel-Lucent
  • iNEMI PB-Free Alloy Characterization Project Report: Part VII – Thermal Fatigue Results for Low-AG Alloys at Extended Dwell Times
    Speaker of DistinctionKeith Sweatman, Nihon Superior Co., Ltd.; Richard Coyle, Ph.D., Alcatel-Lucent; Richard Parker, Delphi; Keith Howell, Nihon Superior Co. Ltd.; Elizabeth Benedetto and Aileen Allen, Hewlett Packard Co.; Joseph Smetana, Alcatel-Lucent; Stuart Longgood, Delphi; Weiping Lui, Indium Corporation and Julie Silk, Agilent Technologies



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