SMTA International  

Conference: Sep. 28 - Oct. 2, 2014  
Exhibition: Sep. 30 - Oct. 1, 2014  

Donald Stephens Convention Center  
Rosemont, IL  

Technical Sessions

Sessions are 1.5 hour programs in which three technical papers are presented under the direction of a chairperson. Each paper is presented by the author on a topic related to the main subject of the session, and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.

Session tracks and symposiums:
Advanced Packaging / Components (AAT)
Business/Supply Chain Issues (BUS)
Evolving Technologies (ET)
Environmental Issues (ENV)
Harsh Environment Applications (HE)
Lead-Free Soldering Technology (LF)
Manufacturing Excellence (MFX)
Process Control (PRC)
SMT Assembly (SMT)
PCB Technology (SUB)
  • 8:30 - 10:00am
  • 10:30am - 12pm
  • 12pm - 1:30pm
  • 1:30 - 3:00pm
  • 3:30 - 5:00pm
  • Tuesday
  • 10:30am - 12:30pm
  • 2:00 - 3:30pm
  • 4:00 - 5:30pm
  • Wednesday
  • 8:00 - 10:15am
  • 10:30am - 12pm
  • 2:00 - 3:30pm
  • 4:00 - 5:30pm
  • Thursday
  • 8:00 - 10:00am
  • 10:30am - 12pm
  • 1:15pm - 2:30pm
  • 3:30pm - 5:00pm

  • Please note that speakers with a Speaker of Distinction icon are recognized as Speakers of Distinction. Over the past 15 years they have been identified by SMTAI attendees as giving the strongest technical presentations. Congratulations to each of these authors for a job exceptionally well done.

    MONDAY, October 14
    8:30am - 10:15am


    Thermal Issues with Harsh Environment Electronics

    Chair: John Evans, Ph.D., Auburn University
    Co-Chair: Charles Bauer, Ph.D., TechLead Corporation
    Monday, October 14 | 8:30am - 10:15am | Room 202A

    This session investigates the challenges of increased temperature for harsh environment electronics. With increased power, reduction of space, and restricted airflows, designers have significant difficulties in meeting operational requirements for harsh environment systems. This session focuses on several solutions for these issues.

  • Thermal Management for FPGAs and 3D Stacks for Space Applications
    Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
  • Improved Prediction of Compressive Forces Required in Thermal Interface Pad Applications
    Jeff Jennings, Harris Corporation
  • New Interconnection for High Temperature Application: HotPowCon (HPC)
    Jörg Trodler, Heraeus Materials Technology GmbH & Co.KG, and Robert Bosch, A. Fix, and Mathias Nowottnick, University of Rostock

    MONDAY, October 14
    10:30am - 12:00pm


    Printed Electronics Technology Status and Implementation Challenges

    Chair: Lee Smith, Plexus Corp.
    Co-Chair: Lars Böettcher, Fraunhofer IZM Berlin
    Monday, October 14 | 10:30am - 12:00pm | Room 203C

    The printed electronics (PE) field is considered to be a compilation of diverse technologies leveraged from several well established industries - graphic arts printing, microelectronics, semiconductor, and nanotechnology- but we need the "out of the box" thinking in implementation. Thus, it is critical to discuss each aspect of these technologies to better define new applications. In this session, the first presenter will discuss various key mixes of technologies engulfing PE technology based on the industry survey and roadmaps. The other two presenters will provide detailed information on specific aspects, i.e. nanomaterials and assembly. Nanomaterials is a key ingredient in ink that enables achieving required characteristic needed for high throughput manufacturing through various printing medium. Assembly by new printing methods are key in successful implementation of the PE at low cost, the key advantage of printed electronics. Join us to learn to take advantage of this growing technology and learn which facets of technologies benefit your company

  • Overview of Industry Roadmaps for Printed Electronics
    Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
  • Commercialization of Nanomaterials and Printed Electronics
    Speaker of DistinctionAlan Rae, Ph.D., NanoMaterials Innovation Center
  • Enabling of Key Manufacturing Platforms by Printed Electronics
    Girish Wable and Dan Gamota, Jabil Circuit, Inc.


    Modeling and Predictions in Harsh Operational Environments

    Chair: Tom Borkes, The Jefferson Project
    Co-Chair: Mike Nadreau, Henkel Electronic Materials LLC
    Monday, October 14 | 10:30am - 12:00pm | Room 202A

    Products that spend a lifetime in harsh operating environments provide the designer AND assembler with a unique set of challenges. The environmental stressing and corresponding reliability of the electronic components that confront the product designer are only a part of this challenge. Our assembly business of "making good solder joints" is confronted with daunting material and process challenges as well. A predictive model that can be validated empirically is the Holy Grail that would provide confidence in establishing a causal relationship between product design and MTBF. This session presents four papers that are significant contributions toward achieving that goal.

  • A Pseudo-Stress, Pseudo-Strain Methodology to Predict Lead-Free Solder Joint Reliability
    Speaker of DistinctionJean Paul Clech, Ph.D., EPSI, Inc.
  • Life Prediction of Lead-Free Electronics Under Simultaneous Automotive Environments of High Temperature and Vibration
    Speaker of DistinctionPradeep Lall, Ph.D., M.B.A., and Geeta Limaye, Auburn University
  • Design for Reliability with Computer Modeling
    Speaker of DistinctionRandy Schueller, Ph.D., DfR Solutions

    MONDAY, October 14
    12:00pm - 1:30pm

    ET Keynote Lunch

    Emerging 3D and TSV Packaging Technology

    Charles Woychik, Ph.D., Invensas Corporation
    Monday, October 14 | 12:15pm - 1:15pm | Room 203C

    MONDAY, October 14
    1:30pm - 3:00pm


    Materials, Materials, Materials

    Chair: Irene Sterian, P.E., Celestica Inc.
    Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Monday, October 14 | 1:30pm - 3:00pm | Room 203C

    We are still continuing to advance materials research and possibilities to address material shortages, as well as material benefits in product assembly and product function. In this session you will learn about the mining of rare earths and the opportunity to recycle these materials, whether nano-copper can be a replacement for solder, and whether hygroscopic silica gel can be used to dissipate high amounts of heat in short time periods. Material advances continue to improve our products!

  • Mining Electronics for Rare Earths
    Speaker of DistinctionAlan Rae, Ph.D., ReNew Rare Earth, Inc.
  • NanoCopper as a Replacement for Solder-A Question of Reliability?
    Peter Borgesen, Ph.D., L. Wentlent, D.P. Schmitz, J. Owens, and R. Prattipati, Binghamton University; A.A. Zinn, E. Hauptfleisch, and D. Blass, Lockheed Martin
  • Silica Gel Coating for Thermal Management of Electronic Components
    Mathias Nowottnick, Felix Bremerkamp, and Dirk Seehase, University of Rostock


    Power Electronics Packaging

    Chair: Pradeep Lall, Ph.D., Auburn University
    Co-Chair: Jean Paul Clech, Ph.D., EPSI, Inc.
    Monday, October 14 | 1:30pm - 3:00pm | Room 202A

    Increased emphasis on energy has resulted in the proliferation of power electronics in hybrid electric and fully-electric vehicles. Examples of automotive applications include the Toyota Prius Hybrid and the high profile launch of the Tesla Model S FEV. Power electronics modules in automotive applications often require high power dissipation and continued operation at high temperature. In this session several packaging technologies targeted for power electronics applications have been presented. Technologies discussed will include embedded components, sintering technologies and hypereutectic solder for die-attach.

  • Power Electronics Packages with Embedded Components-Recent Trends and Developments
    Speaker of DistinctionLars Böettcher, S. Karaszkiewicz, and A. Ostman, Fraunhofer IZM Berlin; D. Manessis, Technical University Berlin
  • Investigations for Sintering Technologies for Power Electronics
    Speaker of DistinctionHans-Juergen Albrecht, Siemens AG
  • Modified Hypereutectic Sn-Cu-Pb-free Solder for Power Semiconductor Die Attach
    Speaker of DistinctionKeith Sweatman, Motanori Miyaoka, Takatoshi Nishimura, Nihon Superior Company, Ltd.; Xuan Quy Tran, Stuart McDonald, Kazuhiro Nogita, University of Queensland

    MONDAY, October 14
    3:30pm - 5:00pm


    Evolving Technologies Panel Covering Key Technologies Including: Embedded Actives/Passives, 3D/TSV, Printed Electronics, Nanotechnology, Advanced Packaging, and Lead-Free Status

    Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
    Co-Chair: Paul Wang, Ph.D., Mitac International Inc.
    Monday, October 14 | 3:30pm - 5:00pm | Room 203C

    Panelists and topics will include:
  • Embedded Active and Passive Technology
    Speaker of DistinctionLars Böttcher, Fraunhofer Institute for Reliability and Microintegration (IZM)
  • Advanced Packaging Technology
    Speaker of DistinctionLee Smith, Plexus Corp.
  • Nanotechnology and Rapid Growth
    Speaker of DistinctionAlan Rae, Ph.D., nanoMaterials Innovation Center
  • EMS Challenges: Meeting New Technology Demand
    Irene Sterian, P.E., Celestica Inc.
  • 3D/TSV Packaging
    Charles Woychik, Ph.D., Invensas Corporation
  • Lead-Free and Reliability
    Speaker of DistinctionPaul Vianco, Ph.D., Sandia National Laboratories


    Lead-Free for High Reliability Applications

    Chair: Scott Nelson, Harris Corporation
    Co-Chair: Debbie Carboni, Kyzen Corporation
    Monday, October 14 | 3:30pm - 5:30pm | Room 202A

    The use of lead-free solder for high reliability applications appears to be on the horizon but is still quite controversial. Papers in this session will focus on using lead-free solder for high performance electronic assembly and what can be done to improve long term reliability.

  • Enhancing Mechanical Shock Performance Using Edgebond Technology
    Steve Perng, TaeKyu Lee, and Cherif Guirguis, Cisco Systems, Inc.
  • Long-term Aging Effects on Reliability Performance of Lead-Free Solder Joints
    Zhou Hai, Jiawei Zhang, Ph.D., Chaobo Shen, Sivasubramanian Thirugnanasambandam, John Evans, Ph.D., M.J. Bozack, and Richard Sesek, Auburn University
  • High Strain Rate Properties of SAC105 and SAC305 Lead-Free Alloys after Extended High Temperature Storage
    Speaker of DistinctionPradeep Lall, Ph.D., M.B.A., and Sandeep Shantaram, Auburn University; David Locker, US Army RDECOM
  • Pb-Free and Halogen-Free Solder for High Reliability Applications
    Gavin Jackson, Ph.D., and Ian J. Wilding, Henkel Ltd.

    TUESDAY, October 15
    10:30am - 12:00pm


    Addressing the Challenges of Emerging Package Technologies

    Chair: Julian Partridge, Ph.D., Flextronics International
    Co-Chair: Mumtaz Bora, Peregrine Semiconductor
    Tuesday, October 15 | 10:30am - 12:30pm | Room 202B

    Leading-edge packages continue to challenge assembly technologists across the packaging hierarchy from the die level up to the connector level. Emerging results and models shed new insight on the impact of process and materials on the reliability of copper wire bonded systems, 2.5D interposer technology with 10,000 I/O micro-bumped die, SiP embedded die polyimide modules, and the solder joint integrity risks of extremely high I/O BGA connectors.

  • Converting High Volume IC Manufacturing to Cu Wire Packages
    Larry Bright, Microsemi
  • Solder Assembly Solutions for 3D IC Packaging
    Charles Woychik, Ph.D., Ellis Chau, Sitaram Arkalgud, Michael Newman, Invensas Corporation
  • Flex Based Embedded Die System in Package Modules
    John Ada and Theodore Tessier, Flip Chip International; Kazuhisa Itoi, Fujukura Electron Device Laboratory
  • High I/O BGA Connector Solder Joint Integrity Investigation
    Speaker of DistinctionDave Hillman, Kim Cho, Jeff Sailor, Ross Wilcoxon, Rockwell Collins


    Challenges and Solutions for Liquid Soldering Processes

    Chair: Ursula Marquez de Tino, Ph.D., Plexus Corp.
    Co-Chair: Peter Biocca, P.E., Kester ITW
    Tuesday, October 15 | 10:30am - 12:00pm | Room 202D

    This session contains a variety of papers on lead tinning, wave, and selective soldering processes. The first paper addresses the development and implementation of a component lead tinning process, use to improve solderability, mitigate tin whiskers, and eliminate gold embrittlement. The second paper provides a summary of a two-year project to study the behavior of various wave solder alloys and proposes a pass/ fail criteria for the copper dissolution metrics. The last paper discusses the next generation of selective soldering machines, design to overcome current challenges on the assembly of thermally challenging boards with fine pitch components

  • Lead Tinning Requirements for the 21st Century
    Roger Cox and Alan Cable, ACE Production Technologies
  • Acceptance Testing of Lead-free Bar Solder Alloys
    Speaker of DistinctionElizabeth Benedetto, Aileen Allen, Kris Troxel, and Jian Miremadi, Hewlett Packard Company
  • Can Selective Soldering Meet Fine Pitch and Other Trends
    Gerjan Diepstraten, Vitronics Soltec BV


    Seamless Sourcing Teams: Best Practices in Information Exchange

    Chair: Susan Mucha, Powell-Mucha Consulting, Inc.
    Co-Chair: Mike Buetow, UP Media Group
    Tuesday, October 15 | 10:30am - 1:00pm | Room 203C

    The quality of IT solutions and internal processes for optimizing production efficiency continue to grow in importance in the outsourcing equation. This session looks at trends and best practices in managing design reviews, production documentation, and material and production status. The session includes a range of perspectives reflecting both supplier solutions and iNEMI’s 2013 Information Management Systems Roadmap.

  • Best Practices for Improving the PCB Supply Chain: Performing the Process Audit
    Cheryl Tulkoff and Craig Hillman, Ph.D., DfR Soultions
  • Accountability Structure in a Contract Manufacturing Engineering Department
    Mike Gerner, Plexus Corp.
  • Developing a Knowledge Based Risk Identification System for Sophisticated SMT Assembly Design and Development
    Jingsong Xie, Ph.D., RelEng Technologies, Inc.
  • Managing Information Across the Supply Chain: Highlights from the iNEMI Roadmap
    Barbara Goldstein, National Institute of Standards and Technology
  • Panel Discussion


    Sustainability and Environmental Regulations

    Chair: Julie Silk, Agilent Technologies, Inc.
    Co-Chair: Cheryl Tulkoff, DfR Solutions
    Tuesday, October 15 | 10:30am - 12:00pm | Room 104

    Sustaining our planet is the goal of the myriad of environmental and social regulations. This session covers strategies for assessing EU RoHS exemptions and mitigating the impact of potential expiration, the reliability of a novel method that allows easy disassembly of printed circuit assemblies so more materials can be recycled, and compliance with imminent conflict minerals regulations, which affect not just public companies, but their entire supply chain.

  • European Union RoHS Recast – Implications for Exemption and Substance Review
    Adam Wheeler, Speaker of DistinctionMarie Cole, Curtis Grosskopf, Jackie Adams, Sophia Lau, Jeff Lagler, Dale Wilhite, and Poh Lin Chong, IBM Corporation
  • Improving Electronics Sustainability With a Novel Reusable, Unzippable, Sustainable Electronics (ReUSE) Interconnect System
    Speaker of DistinctionChrisopher Hunt, Ph.D., and Martin Wickham, National Physical Laboratory
  • Compliance with Conflict Minerals Requirements
    Krista Crotty, Alberi EcoTech

    TUESDAY, October 15
    2:00pm - 3:30pm


    Reliability of Pb-Free Electronic Products Subjected to Harsh Field Conditions

    Chair: Robert Kinyanjui, Ph.D., John Deere Electronic Solutions
    Co-Chair: Guhan Subbrayan, Ph.D., AsteelFlash
    Tuesday, October 15 | 2:00pm - 3:30pm | Room 202A

    Electronic products built for use in harsh environments must meet certain ruggedization tests including but not limited to exposure to programmed severe thermal-stresses, thermo-mechanical and vibrational tests. Pb-Free electronic products present an added challenge due to the requirement for high processing temperature. Thus, material selection, product design and development for Pb-Free products to be used in harsh environments must be guided by careful testing with an eye for survivability.

  • Solder/Metallization Interdiffusion - Case Studies
    Nausha Asrar, Ph.D., Schlumberger
  • Solder Crack Investigations in Real Cases
    Jose Servin Olivares and Cynthia Gomez, Continental
  • The Effect of Pb Mixing Levels on Solder Joint Reliability and Failure Mode of Backward Compatible, High Density Ball Grid Array Assemblies
    Speaker of DistinctionRichard Coyle, Ph.D., Debra Flemming, Richard Popowich, and Peter Read, Alcatel-Lucent, Raiyo Aspandiar, Ph.D., Vasu Vasudevan, Ph.D., and Steve Tisdale, Intel Corporation; Iulia Muntele, Sanmina Corporation


    QFN Package Reliability

    Chair: Rama Hegde, Ph.D., Freescale Semiconductor
    Co-Chair: Viswanadham Puligandla, Ph.D., Nokia (Retired)
    Tuesday, October 15 | 2:00pm - 3:30pm | Room 202B

    The Quad-Flat No-leads (QFN) package is one of the fastest growing package types in the electronics industry today. The QFN, which is in the Bottom Termination Component (BTC) family, offers high I/O density at a relatively low cost. However, some challenges remain with regard to SMT assembly and reliability. In this session, we will review three papers that address improvements to the reliability of QFN, including the array QFN which employs multiple rows to achieve even higher I/O density.

  • The Effect of Coating and Potting on the Reliability of QFN Devices
    Craig Hillman, Ph.D., Greg Caswell and Cheryl Tulkoff, DfR Solutions
  • A Process for Improved QFN Reliability
    Speaker of DistinctionLenora Toscano, Rich Retallick, and John Ganjei, Ph.D., MacDermid, Inc.
  • Reliability Improvement of Array QFN Package
    You Chye How, Texas Instruments Electronics Malaysia Sdn. Bhd.


    Advanced Studies in Bumped Component Reliability

    Chair: Mario Scalzo, Indium Corporation
    Co-Chair: Gregory K. Arslanian, Air Products and Chemicals, Inc.
    Tuesday, October 15 | 2:00pm - 3:30pm | Room 202D

    In very recent years, BGA, CSP and other bumped components are not only becoming more complex, but also increasingly more mission-critical for high-reliability applications. Add to this the difficulties and limitations during the assembly process and it is no surprise that manufacturers have questions and concerns. This session will discuss said assembly processes and the issues caused by miniaturization, new alloys and increasing pressures to reduce material costs, and their effect on reliability.

  • Impact of Low Silver Solder Pastes on Area Array Solder Joint Quality
    Srinivas Aravamudhan, Dudi Amir, Lilia May, Ph.D., P.E., Scott Mokler, Suddhasattwa Nad, and Raiyo Aspandiar, Ph.D., Intel Corporation
  • Voiding and Reliability of BGA Assemblies With SAC and 57Bi42Sn1Ag Alloys
    Yan Liu, Joanna Keck, Erin Page, and Speaker of DistinctionNing-Cheng Lee, Ph.D., Indium Corporation
  • Effects of Materials, Design and Process on Intermetallic Formation and Evolution in Solder Microbumps
    K. Schnabl, L. Wentlent, E. Perfecto, P. Borgesen, Ph.D., Binghamton University; M. Lu, IBM Corporation


    Process Development for Miniaturized and High Reliability Electronics

    Chair: Tim Jensen, Indium Corporation
    Co-Chair: Brenda Estrada-Schmidt, Raytheon Systems Company
    Tuesday, October 15 | 2:00pm - 3:30pm | Room 202C

    Material and process characterization is a critical aspect toward maximizing electronics assembly yields and reliability. As 60 to 70 percent of all defects can be associated with the printing process, it is necessary to optimize the stencil design and printer set-up as well as carefully select the solder paste that will be used. The advancement of electronics toward smaller and more reliable has put an even greater emphasis on proper material selection and process optimization.

  • Stencil Evaluation and Solder Paste Inspection Accuracy Assessment for Miniaturized SMT Components
    Robert Farrell, Benchmark Electronics, Inc. and Speaker of DistinctionChrys Shea, Shea Engineering Services
  • Evaluation of Solder Pastes for High Reliability Applications
    Scott Anson, Ph.D., P.E., LeTourneau University; Michael McLaughlin, Rochester Institute of Technology, Abner Argueta, IEC Electronics Corporation
  • Stencil Aperture Design Considerations for 0.3 CSP Ultra-Fine Pitch Printing
    Speaker of DistinctionMark Whitmore and Jeff Schake, DEK Printing Machines Ltd.

    TUESDAY, October 15
    4:00pm - 5:30pm


    Manufacturing for Harsh Environments

    Chair: Scott Priore, Cisco Systems, Inc.
    Co-Chair: Rod Howell, Libra Industries, Inc.
    Tuesday, October 15 | 4:00pm - 5:30pm | Room 202A

    In today’s world we need to understand many different factors that influence reliability of the products we build. One such factor is the product's ability to resist corrosion of various types. This session will address corrosion concerns with the solder alloys we use and how cleanliness effects the product reliability. The last paper will demonstrate the use of Weibull analysis to ensure we are accurately predicting our product's life expectancy meet the customer’s demands.

  • Corrosion Resistance of High Melting Lead-Free BiAgX Solder Joints
    Hongwen Zhang and Speaker of DistinctionNing-Cheng Lee, Ph.D., Indium Corporation
  • Copper Corrosion Effects from Cleaning Agent Entrapment
    David Lober and Speaker of DistinctionMike Bixenman, DBA, Kyzen Corporation; Linda Woody, Lockheed Martin
  • Using Weibul Analysis to Interpret Failure Data in Electronics Assembly Stress Testing
    Speaker of DistinctionRon Lasky, Ph.D., P.E., Indium Corporation


    Pad Cratering

    Chair: Randy Schueller, Ph.D., DfR Solutions
    Co-Chair: Evstatin Krastev, Ph.D., Nordson DAGE
    Tuesday, October 15 | 4:00pm - 5:30pm | Room 202B

    Pad cratering is widely recognized as one of the dominant mechanical failure mechanisms with area array components using Pb-free solder such as SAC305. The papers in this session will discuss variables such as laminate strength, stiffness, strain rate, standoff height and pad design on the tendency for pads to crater. A better understanding of this failure mechanism will enable users to improve the durability of their assemblies.

  • Stain Rate and Cyclic Strain Dependencies of PWB Pad Crater Susceptibility
    Speaker of DistinctionJohn McMahon, P.E., Brian Standing, and Michael Thompson, Celestica Inc., and Jim Wilcox, Derek Robertson, and Speaker of DistinctionMatt Kelly, P.Eng., MBA, IBM Corporation
  • Comparing LGA and BGA Assemblies in Terms of Solder Pad Cratering
    Pericles Kondos, Ph.D., and Martin Anselm, Ph.D., Universal Instruments; Y. Zeng, J. Jiang, and Peter Borgesen, Ph.D., Binghamton University
  • Investigation on Pad Crater Failure of BGA Solder Joints
    Luo Daojun, Zou Yabin, and He Guanghui, China CEPREI Laboratory


    Conformal Coating: The Next Level for High Reliability in Harsh Environments

    Chair: Jason Keeping, P.E., Celestica Inc.
    Co-Chair: TBD
    Tuesday, October 15 | 4:00pm - 5:30pm | Room 202D

    Conformal Coating is becoming a more essential process with the increasing market requirements and demands to reduce total production costs, while still maintaining high reliability for the various environments within the industry. Some of these key reliability factors will be discussed; coverage & thickness, physical & chemical compatibility, along with adhesion. Thus, knowledge on these evolving factors and their interactions are key for anyone to have success in this sector.

  • Conformal Coating 101: General Process Overview, Process Development and Control Methods
    Speaker of DistinctionAlexander Zeitler and Dave Jensen, BTW, Inc.
  • Overcoming the Challenges Presented with Automated Selective Conformal Coating of Advanced Electronic Assemblies by Employing Plasma Treatment Technology
    David Foote, Nordson MARCH
  • Case Study: Tools to Assure Compatibility of Conformal Coatings and No-Clean Lead-Free Solder Pastes
    Emmanuelle Guene, P.E., and Celine Puechagut, Inventec Corporation


    Performance of Stencil Applied Coatings

    Chair: Jeff Schake, DEK USA
    Co-Chair: Brook Sandy-Smith, Indium Corporation
    Tuesday, October 15 | 4:00pm - 5:30pm | Room 202C

    As component assembly density continues trending to finer dimensions, successful stencil printing demands stricter tolerances on equipment setup, solder paste material, and stencils. One recent innovation generating much industry buzz is the specially engineered stencil applied coatings that claim to achieve printing capability improvement. With the stencil marketplace now offering a variety of unique chemical coatings on laser cut solder paste printing stencils, this session offers comprehensive review of this technology and performance results.

  • Fine Tuning the Stencil Manufacturing Process and Other Stencil Printing Experiments
    Speaker of DistinctionChrys Shea, Shea Engineering Services; Ray Whittier, Vicor Corporation-VI Chip Division
  • Can Nano Coatings Really Improve Stencil Performance?
    Tony Lentz, FCT Assembly, Inc.
  • Plasma Stencil Treatments: A Statistisical Evaluation
    Speaker of DistinctionMatt Kelly, P.E., MBA, William Green, Speaker of DistinctionMarie Cole, and Ruediger Kellman, IBM Corporation

    WEDNESDAY, October 16
    8:00am - 10:00am


    Development and Optimization of 0.3mm Pitch BGA Packages for Mobile Applications

    Chair: Charles Woychik, Ph.D., Invensas Corporation
    Co-Chair: Andrew Mawer, Freescale Semiconductor
    Wednesday, October 16 | 8:00am - 9:30am | Room 202B

    The continuing trend of miniaturization puts increased emphasis on process solutions for a robust assembly. The wide application of PoP and the adoption of less than 0.4mm pitch CSPs in smartphones and tablets are challenging current design rules and material sets. This session will cover factors such as PCB design, paste printing parameters, dip and place processes and alloy selection for the successful integration of advanced components.

  • Progression to 0.3 mm Pitched BGA SMT Assembly
    Michael Kochanowski, Intel Corporation
  • Demonstrated Process and Reliability of 0.35mm Pitch BGA Devices for Mobile Environment
    Speaker of DistinctionBrian Roggeman, Alan Choi, and Mark Schwartz, Qualcomm Technologies Inc.
  • Manufacturability Assessments of Board Level Adhesives on Fine Pitch Ball Grid Array Components
    Venmathy Rajarathinam, Ph.D., James Wade, Alan Donaldson, Raiyo Aspandiar, Ph.D., Devadoss Chelladurai, and Scott Mokler, Intel Corporation


    Reliability of Low Silver Alternatives to SAC Alloys

    Chair: Brian Toleno, Ph.D., Henkel Electronic Materials LLC
    Co-Chair: Keith Howell, Nihon Superior Company, Ltd.
    Wednesday, October 16 | 8:00am - 9:30am | Room 202D

    The electronics industry move from tin lead to Pb-free alloys has focused mainly on tin-silver-copper (SAC) alloys with the silver content in the 3% range to replace the long-used Sn63 solders. In this session several authors will discuss the reasons and challenges with implementing these newer alloys. Specifically, lower silver versions of the SAC alloy are known to provide some cost savings due to the lower amount of silver, but the lower silver content impacts drop test reliability which is critical to performance (especially in mobile devices). The first three papers describe different micro-alloying additives that can be used to increase the reliability of these low and no silver alloys. The final paper addresses one of the other aspects of moving to the SAC alloys, which is the higher melt temperatures effect on the solder inside of packages. The last paper discussed the performance and reliability aspects of Pb-free solder options inside of system in package devices.

  • A Study of Lead-Free, Low Silver Solder Alloys with Nickel Additions
    Speaker of DistinctionJasbir Bath, Bath and Associates Consultancy LLC; Munehiko Nakatsuma, Takehiro Wada, Kimiaki Mori, Koichi Shimokawa, Takeshi Shira, Atsushi Irisawa, Roberto Garcia, Koki Limited
  • Lead-Free Antimony-Based Alloy Characterization
    Siew Kee Lee and YS Khoo, Texas Instruments Electronics Malaysia Sdn.Bhd.
  • Production Testing of Ni-Modified SnCu Solder Paste
    Karl Seelig, Timothy O'Neill, Kevin Pigeon and Mehran Maaleckian, AIM Solder; Andy Monson and Wlater Machado, Hayward Industries HRI (formerly Goldline Controls); Speaker of DistinctionChrys Shea, Shea Engineering Services
  • The Second Generation Shock Resistant and Thermally Reliable Low Ag SAC Solder Doped With Mn
    Vahid Goudarzi and Matthew Brown, Motorola Mobile Inc.; Weiping Liu and Speaker of DistinctionNing-Cheng Lee, Ph.D., Indium Corporation; Jeffrey ChangBing Lee, IST-Integrated Service Technology Inc.


    BGA Profiling and Reballing

    Chair: Robert Farrell, Benchmark Electronics, Inc.
    Co-Chair: Glenn Robertson, Process Sciences Inc.
    Wednesday, October 16 | 8:00am - 9:30am | Room 202C

    Non-destructive BGA profiling is frequently required for prototype assembly, rework, and field service returns. Results from non-destructive BGA profiling are compared with destructive methods. BGA reballing allows a component to be reused or Pb-Free spheres to be replaced with SnPb. A method to reball fine pitch BGAs is presented and the reliability of reballed BGA is assessed.

  • 01005 Passive Component Rework
    Ronald Wachter, Air-Vac Engineering Co.
  • Ultra-Fine Pitch Deballing and Reballing - What Needs to Change
    Bob Wetterman, BEST, Inc. and Don Naugler, VJ Electronix, Inc.
  • Effect of BGA Re-Balling and its Influence on Ball Shear Strength and Board Level Reliability
    Speaker of DistinctionS. Manian Ramkumar, Ph.D., and Andrew Daya, Rochester Institute of Technology


    PCB Fabrication and Reliability

    Chair: Robert Kinyanjui, Ph.D., John Deere Electronic Solutions, Inc.
    Co-Chair: Srini Aravamudhan, Intel Corporation
    Wednesday, October 16 | 8:00am - 9:30am | Room 204A

    Proper design and fabrication of both rigid and flexible printed circuit boards is critical to ensuring reliable board assembly electronic products. The plated through hole via (PTV) is a key structure of a PCB, and therefore requires that it be designed using fundamental materials science principles. Fabrication defects within PTVs can impair board reliability. Delamination is a common PCB defect and ways to mitigate it need to be comprehended.

  • Reliable Plated Through-Via Design and Fabrication
    Cheryl Tulkoff, and Craig Hillman, Ph.D., DfR Solutions, Inc.
  • Investigation on Root Cause for Via with Solder Bubble
    Wang Yang and Luo Daojun, China CEPREI Laboratory
  • Impact of FPC Fabrication Process on SMD Reliability
    Susie Krzmarzick, John Dzarnoski, Ph.D., and Yangjun Xing, Ph.D., Starkey Hearing Technologies

    WEDNESDAY, October 16
    10:30am - 12:30pm


    Advances in PoP: Process and Reliability

    Chair: Brian Roggeman, Qualcomm Inc.
    Co-Chair: Ben Zarkoob, Amkor Technology
    Wednesday, October 16 | 10:30am - 12:30pm | Room 202B

    Consumer electronics drive miniaturization, and PoP is a common solution. The successful integration of PoP can depend on many factors, including package construction, warpage, SMT process, material sets and environment. A detailed look at several of these variables, including a novel PoP package style will be presented.

  • Effect of Warpage on SMT Process of PoP Package and Its Solution
    Alex Chen, Stephen Guo, Fubin Song, Jeff Qi, and James Huang, Celestica Inc.
  • Predicting the Reliability of Package-on-Package Interconnections Using Computational Modeling
    Speaker of DistinctionPaul T. Vianco, Ph.D., Michael K. Neilsen, Jerome A. Rejent, J. Mark Grazier, and Alice C. Kilgo, Sandia National Laboratories
  • Process and Material Envelope for Allowable Package-on-Package Warpage
    Speaker of DistinctionPradeep Lall, Ph.D., Kewal Patel, and Vikalp Narayan, Auburn University
  • Higher Density PoP Semiconductor Packaging Solution: Bridging the Infrastructure Gap Between Wire-Bond and TSV Interconnect
    Speaker of DistinctionVern Solberg, Charles Woychik, Ph.D., Wael Zohni, and Ilyas Mohammed, Invensas Corporation


    Alloy Selection and its Influence on Electronic Assembly

    Chair: Ray Chartrand, CharTrain Consulting, Inc.
    Co-Chair: Peter Biocca, P.E., Kester ITW
    Wednesday, October 16 | 10:30am - 12:00pm | Room 202D

    How do you select an alloy to meet your manufacturing needs? One choice is simple, leaded or non-leaded. From there, the choices are myriad. Listen to three industry experts discuss the selection, development and mechanical properties of solder alloys.

  • Effect of Variation in the Reflow Profiles of Pb Free Solder on Lifetimes In Room Temperature Fatigue Tests
    Francis Mutuku and E.J Cotts,Ph.D., Binghamton University; Babak Arfaei, Ph.D. and Martin Anselm, Ph.D, Universal Instruments Corporation
  • Low Temperature Alloy Development for Electronics Assembly – Part II
    Rahul Raut, Morgana Ribas, Sujatha Chegudi, Anil Kumar, Ranjit Pandher, Sutapa Mukherjee, Siuli Sarkar, and Bawa Singh, Alpha, an Alent plc Company
  • Alternative Lead Free Alloys for SMT Assembly
    Karl Seelig, AIM


    Advances in Reflow Soldering

    Chair: Ray Whittier Jr., Vicor Corporation
    Co-Chair: Brenda Estrada-Schmidt, Raytheon Systems Company
    Wednesday, October 16 | 10:30am - 12:30pm | Room 202C

    Reflow soldering is the process by which nearly every SMT solder joint is formed, and is critical to the performance and reliability of PCB assemblies. Due to its criticality, research is continuously underway to characterize and improve the process. Studies presented in this session include new methods of measuring wetting and spread, the effects of thermal profiles on the microstructures of SAC solder joints, considerations in low silver SAC solders, and low temperature pin-in-paste reflow of tin-bismuth solders as an alternative to wave soldering.

  • Characterization of Solder Paste Wetting/Spreading Performance-Current Status in International Norms and Standards
    Sebastian Stengel, and Marcus Reichenberger, Ph.D., Georg-Simon-Ohm Hochschule, Albert Heilmann and Jörg Trodler, Heraeus Materials GmbH
  • The Effect of Variation in the Reflow Profile on the Microstructure and Mechanical Behavior of Near Eutectic SnAgCu Alloys
    Francis Mutuku, E.J Cotts, Minhu Lu, and Eric Perfecto, Binghamton University
  • Alloy and Process Optimization for Low Ag Solders
    Speaker of DistinctionTimothy Jensen, and Ed Briggs, Indium Corporation
  • Eliminating Wave Soldering with Low Melting Point Solder Paste
    Mitch Holtzer and T.W. Mok, Alpha, an Alent plc Company


    Printed Circuit Board Performance and Reliability

    Chair: Don Banks, St. Jude Medical
    Co-Chair: Viswam Puligandla, Ph.D., Nokia (Retired)
    Wednesday, October 16 | 10:30am - 12:00pm | Room 204A

    Printed circuit board (PCB) materials play a key role in the viability of finished microelectronic assemblies. In this session, electrical performance as a function of environmental conditions is examined. Next, reliability of plated vias is quantified for different Pb-free compatible laminate/resin combinations using interconnect stress testing (IST). The final paper shares the High Density Packaging Users Group Consortium work on plated through-hole reliability (by IST) on PCBs made with 24 different materials.

  • Electrical Performance of High-Frequency Laminates as a Function of Temperature and Humidity
    Brian Wright, Agilent Technologies
  • Lead-Free Laminate DMA and TMA Data to Develop Stress Versus Temperature Relationship for Predicting Plated Hole Reliability
    Stepanie Moran and Michael Freda, Oracle; Joseph Smetana, Alcatel-Lucent
  • Materials Testing of PWB Substrates to Determine Survivability Through Lead Free Assembly
    Bill Birch and Jason Furlong, PWB Interconnect Solutions Inc.

    WEDNESDAY, October 16
    2:00pm - 3:30pm


    Wafer Level and Flip Chip Package Reliability

    Chair: Andrew Mawer, Freescale Semiconductor
    Co-Chair: Lars Böettcher, Fraunhofer IZM Berlin
    Wednesday, October 16 | 2:00pm - 3:30pm | Room 202B

    This session will explore various aspects of Wafer Level and Flip Chip area array package reliability at both the package and the board level. Board mounted drop test and thermal cycling reliability will be investigated, including the evaluation of different Pb-Free alloys, through both testing and simulation. At the component level, the interaction between the die’s brittle low-k and ultra-low-k (ULK) dielectrics and the package materials is investigated through testing and modeling.

  • Thermal Cycle Fatigue Life Model for WLCSP Solder Joints
    Speaker of DistinctionRobert Darveaux, Ph.D., Skyworks Solutions, Inc.
  • Effects of Test Condition and System Design on Wafer Level Package Drop Test Reliability
    Tiao Zhou, Ph.D., Maxim Integrated; Xuejun Fam, Lamar University
  • 3-D Fracture Analysis of the BEoL Region of a Flip Chip Package During Die Attach Process
    Zaeem Baig, Fahad Mirza, Hardik Parekh, and Dereje Agonafer, Ph.D., Unversity of Texas at Arlington


    PCB Cavity or Inner Layer Component Assembly

    Chair: Dale Lee, Plexus Corp.
    Co-Chair: Rich Henrick, Sanmina Corporation
    Wednesday, October 16 | 2:00pm - 3:00pm | Room 202D

    The use of cavities or inner layer component attachment in printed circuit boards for electronic assembly has been used for many years to improve assembly density, functional performance and/or operational reliability. With the increased demands to provide more and more functionality into smaller areas, increased use of Z-axis assembly into cavities are being utilized as a potential solution. New methods for formation of cavities and assembly are evolving to meet these needs.

  • Benefits and Challenges of Manufacturing with Printed Circuit Board Cavities
    Pedro J. Martinez, William Alger, and Weston C. Roth, Intel Corporation
  • High Density Assembly in PCB Cavities
    Speaker of DistinctionJonas Sjoberg and Ranilo Aranda, Flextronics Advanced Engineering Group


    BTCs: Voiding, Cleaning and Other Assembly Considerations

    Chair: Chrys Shea, Shea Engineering Services
    Co-Chair: Ray Whittier, Vicor Corporation
    Wednesday, October 16 | 2:00pm - 3:30pm | Room 202C

    Bottom Termination Components, or BTCs, are the fastest growing package type in SMT technology and bring many varied and unique challenges to PCB assemblers. Optimizing designs and processes to maximize joint quality, minimize voiding, enable effective cleaning and ensure reliable performance require careful consideration of a multitude of factors. This session discusses the effects of component footprint, thermal pad design, stencil design, reflow profiling and cleaning materials & equipment on BTC assembly processes.

  • Voiding Mitigation for Bottom Termination Components
    Jennifer Nguyen, David Geiger and Murad Kurwa, Flextronics International
  • QFN Design Considerations to Improve Cleaning
    Speaker of DistinctionMike Bixenman, DBA, Kyzen Corporation; Speaker of DistinctionDale Lee, Plexus Corp.; Speaker of DistinctionSteve Stach, Austin American Technology Corporation, and Bill Vuono, Raytheon Systems Company
  • Optimizing Assembly of QFNs
    Brook Sandy-Smith and Seth Homer, Indium Corporation


    Investigation of Reliability for Alternate Surface Finishes

    Chair: Lenora Toscano, MacDermid, Inc.
    Co-Chair: Barry Hindin, Ph.D., P.E., Battelle Laboratories
    Wednesday, October 16 | 2:00pm - 3:30pm | Room 204A

    Since the transition to lead-free surface finishing there has been strong focus on reliability and investigation to find one finish that will serve all end use requirements. The exploration continues. This session will investigate the reliability concerns associated with conventionally used surface finishes, specifically OSP and ENIG. It will also discuss the future with introductions of new alternatives more recent to the market.

  • Is a High Phosphorus Content in the Nickel Layer a Root Cause for "Black Pad" on ENIG Finishes?
    Joe McGurran, Mustafa Oezkoek, Ph.D., P.E., Kenneth Lee, and Britta Schafsteller, Atotech GmbH
  • Characteristics of Electroless Palladium/Immersion Gold (EPIG) Deposits for Use in Fine Line Applications
    Speaker of DistinctionDon Gudeczaukas, Katsuhisa Tanabe, and Shigeo Hashimoto, Uyemura International Corporation
  • Manufacturability Assessment of Next Generation PCB Surface Finishes
    Sue Teng, Scott Priore, and Jennifer Oliver, Cisco Systems, Inc.


    Process Inspection Technologies

    Chair: Terry Kocour, Schlumberger
    Co-Chair: Denis Jean, Plexus Corp.
    Wednesday, October 16 | 2:00pm - 3:30pm | Room 201B

    Effective process controls requires an understanding of the elements and process variables which reduce the service life of an assembly. Advanced Non-destructive testing and inspection techniques can be deployed in-house or by an outside analytical laboratory for failure analysis and process control.

  • Understanding Electrical Leakage and Electrochemical Migration In Electronics
    Speaker of DistinctionEric Camden, Foresite
  • Measuring Tiny Solder Deposits With Accuracy and Repeatability
    Brook Sandy-Smith, Indium Corporation; Joe Perault, Parmi USA
  • A Method for Quickly Evaluating Aluminum Pad Corrosion
    Terence Collier, CV Inc.

    WEDNESDAY, October 16
    4:00pm - 5:30pm


    The Impact of the Process Environment on Solder Defects

    Chair: Dave Hillman, Rockwell Collins
    Co-Chair: William Coleman, Ph.D., Photo Stencil
    Wednesday, October 16 | 4:00pm - 5:30pm | Room 202B

    The typical electronics process environment can be a brutal and torturous world to components. Process environments include not only specific inert atmospheres used in reflow soldering but the "hidden procedures" such as component storage, adhesive curing or moisture removal baking. This session focuses on three specific topic areas - component oxidation (storage environment impact), component processing (moisture baking impact) and reflow atmosphere (assembly process impact) - where correct topic management can improve your assembly yields.

  • Solderability and Oxide Thickness Measurement to Determine Long Term Storage of BGAs and QFPs
    Rama Hegde, Ph.D., Terry Burnette, and Speaker of DistinctionAndrew Mawer, Freescale Semiconductor
  • Impact of Component Bake on Solder Joint Quality
    Lilia May, Ph.D., P.E., Dudi Amir, Srinivasa R. Aravamudhan, Christopher Kovalchick, Rajen Sidhu, Suddhasattwa Nad, and Wade Hezeltine, Intel Corporation; Garrett D. Cogburn, Oregon State University
  • Facilitating the Reduction of Head-in-Pillow Defects and Improving Assembly Reliability & In-line Productivity using Nitrogen Reflow
    Maeva Tureau, Ph.D., Air Products and Chemicals, Inc.


    Advancements in Cleaning Process Controls

    Chair: Jason Keeping, P.E., Celestica Inc.
    Co-Chair: Michael Konrad, Aqueous Technologies Corporation
    Wednesday, October 16 | 4:00pm - 5:30pm | Room 202C

    Cleaning is becoming a more complex operational process with the migration from PTH & SMT component technologies to the newer package types such as BGA & QFN's along with the industry conversion from Tin-Lead to Lead-Free among other green materials. These cleaning complexities can be seen throughout the entire assembly process. Thus, a new series of process control methods were required and developed.

  • Electronic Assembly Misprint Cleaning Advancements
    Speaker of DistinctionMike Bixenman, DBA, Kyzen Corporation; Dirk Ellis, Jim Morris and Greg Calvo, Speedline Technologies
  • Concentration Monitoring & Closed Loop Control – A Technological Advancement
    Umut Tosun and Axel Vargas, ZESTRON America; Bryan Kim, Ph.D., Pressure Products Company, Inc.
  • Capillary IC-A New Platform for Detection of Ionic Compounds on Electronic Components
    Peter Bodsky, Kirk Chassinol, and Bob Joyce, ThermoFisher Scientific


    Substrate Technologies for Advanced Electronics

    Chair: Laura Turbini, Ph.D., International Reliability Consultant
    Co-Chair: Patrick Ryan, Indium Corporation
    Wednesday, October 16 | 4:00pm - 5:30pm | Room 204A

    With the drive toward increased functionality and reduced size, weight and power, printing wiring board technology continues to evolve. Alternative substrate materials including thin, particle-containing organics, liquid crystal polymers and microflex substrates have been introduced along with very thin electrodeposited copper. Buildup multilayer boards provide coreless substrates which minimize warpage. These technologies will be discussed in this session.

  • Advanced Organic Substrate Technologies to Enable Extreme Electronics Miniaturization
    Susan Bagen, P.E., Dave Alcoe, Frank Egitto, Steve Rosser, Rabindra Das, Kim Blackwell, and Glen Thomas, Endicott Interconnect Technologies, Inc.
  • Warpage Mitigation Processes in the Assembly of Large Body Size Mixed Pitch BGA Coreless Packages for Use in High Speed Network Applications
    John Savic and Weidong Xie, Cisco Systems, Nokibul Islam, Mukul Joshi, GunOH Park, and KyungOe Kim, STATS ChipPAC Ltd.
  • Ultra Flat and Almost No Profile ED-Copper Foils for High Speed Digital PCBs and Chip Scale Packaging
    Raymond Gales, Circuit Foil


    Imaging, Inspection, and Quality

    Chair: Kaye Porter, GDCA, Inc.
    Co-Chair: Dock Brown, Medtronic (Retired)
    Wednesday, October 16 | 4:00pm - 5:30pm | Room 201B

    In order to reduce manufacturing costs and repair time, the ability to locate potential defects is critical for an effective quality assurance program. As part of a comprehensive production processes, non-destructive testing such as X-ray and scanning can be used to inspect encapsulated microelectronics and assembly without destroying expensive boards or components. Once gathered, this data can then be used to create real-time, detailed diagnostic assessments and predict potential failure risks.

  • Transducer and System Dependency of Scanning Acoustic Microscope Images for Plastic Encapsulated Microelectronics
    Stephen Hwang, Ph.D., Sandia National Laboratories
  • 2D/3D X-Ray Inspection: Process Control and Development Tool
    Zhen (Jane) Feng, Ph.D., Tho Vu, Michael Xie, Speaker of DistinctionDavid Geiger, and Murad Kurwa, Flextronics International Inc., Zohair Mehkri, Santa Clara University; Evstatin Krastev, Ph.D., Nordson DAGE
  • Fix the Process Not Just the Product
    Mary Elmallakh, Digitaltest

    THURSDAY, October 17
    8:00am - 10:00am


    New Technologies for the Detection of Counterfeit Components

    Chair: Robert Flores, Air Force Supply Chain Risk Management
    Co-Chair: Kaye Porter, GDCA, Inc.
    Thursday, October 17 | 8:30am - 10:00am | Room 204B

    Counterfeit components have been linked to disastrous consequences in applications ranging from medical to industrial electronic systems. The ubiquitous nature of counterfeit electronic components in our supply chain has greatly increased the need for counterfeit detection technologies. This session will explore new concepts and technologies being used today to find fake components before their insertion in final product.

  • Counterfeit Avoidance International Certification to AS 5553A, AS 6081, AS 6174
    Stanley Salot, Jr., ECC Corporation
  • JetEtch CuPROTECT and Copper IC Inspection
    Erik Jordan Nisene Technology Group
  • Data Fusion for Augmented Electronic Counterfeit Detection Efficacy
    Bill Cardoso, Ph.D., Creative Electron; Jose Barnabe, SpaceX


    Printed Circuit Board Technology in a Pb-free Electronics Industry: A Report by the High Density Packaging Users Group (HDPUG) Consortium

    Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Co-Chair: Matthew Kelly, P. Eng., MBA, IBM Corporation
    Thursday, October 17 | 8:30am - 10:00am | Room 204A

    The advent of Pb-free soldering technology has driven the printed circuit board (PCB) industry to pay closer attention to the effects of new materials and processes on the performance and reliability of current and next-generation laminates. The High Density Packaging Users Group (HDPUG) consortium is at the forefront of research activities that directly support the PCB supply chain in an effort to meet these objectives. Critical topics include the sensitivity of laminates to delamination and pad cratering as well as conditions that cause conductive anodic filament (CAF). The PCB manufacturing and process engineers are having to address these and other challenges for advanced laminate designs that have higher feature densities, ever-increasing layer counts, and survive Pb-Free second level assembly processes

  • Reliability Testing of PWB Plated Through Holes Using Interconnect Stress Testing Thermal Cycling Before and After Pb-Free Reflow Preconditioning
    Bill Birch, PWB Interconnect Solutions, Inc.
  • Impact of Pb-free Assembly on Laminate Electrical Performance for High Layer Count High Reliability PCBs
    Gary Long, Gary Brist,and Deassy Novita, Ph.D., Intel Corporation
  • Conductive Anodic Filament (CAF) Performance of PWB Materials Before and After Pb-Free Reflow
    Joe Smetana, Alcatel-Lucent, Kim Morton, Viasystems, and Thilo Sack, Celestica Inc.

    THURSDAY, October 17
    10:30am - 12:00pm


    Counterfeit Components and Supply Chain Management

    Chair: Bill Cardoso, Ph.D., Creative Electron
    Co-Chair: Erik Jordan, Nisene Technology Group
    Thursday, October 17 | 10:30am - 12:00pm | Room 204B

    The influx of counterfeit electronic components in our supply chain is an ever-increasing threat to our economy. The latest report issued by the US Department of Commerce states that the number of counterfeit incidents almost tripled between 2005 and 2008. This counterfeit threat is a ubiquitous problem that requires a serious overview of supply chain best practices. From military to commercial applications, counterfeit components have claimed billions of dollars in losses.

  • Simplifying the Complexities of Component Counterfeit Detection
    Dave Loaney, Premier Semiconductor Services, LLC
  • In Search of a Counterfeit Risk Mitigation Strategy: Lessons Learned in Review of the Current State of the Electronics Industry as Regards Counterfeit Mitigation Requirements for Suppliers
    Kevin Sink, TTI, Inc.
  • Legacy Management: Cross-Industry Sustaining Engineering and Managing Obsolescence Counterfeit Risk
    Kaye Porter, GDCA, Inc.


    Lead-Free Alloys, Surface Finishes, and Reliability Impacts

    Chair: Matthew Kelly, P. Eng., MBA, IBM Corporation
    Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Thursday, October 17 | 10:30am - 12:00pm | Room 204A

    This session focuses on latest industry data reported by DfR Solutions and iNEMI relating to effects of gold embriddlement in lead-free interconnects and dwell time on SMT solder joint thermal fatigue performance using SnAgCu and alternate lead-free alloys. Examination of surface finish, alloy, cycle conditions, and microstructures will be reported.

  • iNEMI Pb-Free Alloy Characterization Project Report: Part V - The Effect of Dwell Time on Thermal Fatigue Reliability
    Speaker of DistinctionRichard Coyle, Ph.D., Alcatel-Lucent, Richard Parker and Stuart Longgood, Delphi; Michael Osterman, CALCE; Speaker of DistinctionKeith Sweatman and Keith Howell, Nihon Superior; Speaker of DistinctionElizabeth Benedetto and Aileen Allen, Hewlett Packard; Joelle Arnold, DfR Solutions
  • iNEMI Pb-Free Alloy Characterization Project Report: Part VI-The Effect of Component Surface Finishes and Solder Paste Composition on Thermal Fatigue of Sn100C Solder Balls
    Speaker of DistinctionRichard Coyle, Ph.D., Alcatel-Lucent, Ricahrd Parker and Stuart Longgood, Delphi; Speaker of DistinctionKeith Sweatman and Speaker of DistinctionKeith Howell, Nihon Superior; Babak Arfaei, Universal Instruments
  • Gold Embrittlement in Lead-Free Solder
    Craig Hillman, Ph.D., Nathan Blattau, Joelle Arnold, Thomas Johnston, and Stephanie Gulbrandsen, DfR Solutions; Julie Silk and Alex Chiu, Agilent Technologies

    THURSDAY, October 17
    1:15pm - 3:00pm


    Miniaturization Effects on Pb-free Process, Reliability, and Reworkability - AREA (Advanced Research in Electronic Assembly) Consortium

    Chair: Richard Coyle, Ph.D., Alcatel-Lucent
    Co-Chair: Keith Sweatman, Nihon Superior Company, Ltd.
    Thursday, October 17 | 1:15pm - 3:00pm | Room 204A

    As the transition to Pb-free manufacturing proceeds, the consumer electronics market continues to introduce new assembly and reliability challenges. These include implementing advanced, finer pitch devices, the PCB technology required to route those devices, and rework concerns for high cost devices. This session addresses some of the reliability and assembly challenges presented by these advanced packaging issues.

  • A Roadmap of Technology and Reliability Characterization
    Speaker of DistinctionDenis Barbini, Ph.D., and Martin Anselm, Ph.D., Universal Instruments Corporation
  • Fine Pitch Reliability Comparisons Between Components Assembled on Motherboards With Filled and Unfilled Microvia-in-Pad
    Michael Meilunas and Martin Anselm, Ph.D., Universal Instruments Corporation
  • Effect of Sn Grain Morphology on Reliability of Lead-Free Solder Joints in Thermal Cycling Tests
    Babak Arfaei, Ph.D., and Martin Anselm, Ph.D., Universal Instruments Corporation, Shantanu Joshi, Sam Mahin-Shirazi, Eric Cotts, and Peter Borgesen, Ph.D., Binghamton University, James Wilcox, IBM Corporation; Speaker of DistinctionRichard Coyle, Ph.D., Alcatel-Lucent, Ltd.
  • Fine Pitch Re-ball and Reliability
    Harry Schoeller, Ph.D., and Michael Meilunas, Universal Instruments Corporation

    THURSDAY, October 17
    3:30pm - 5:00pm


    Actively Improving Your Soldering Process

    Chair: Dave Hillman, Rockwell Collins
    Co-Chair: Kola Akinade, Ph.D., Cisco Systems, Inc.
    Thursday, October 17 | 3:30pm - 5:00pm | Room 204A

    Today's soldering processes are in a state of consistent revision. New materials, changes in process consumables and new technologies offer a path forward in terms of making your soldering process more repeatable and consistent. This session focuses on three topic areas - next generation solder pastes, nitrogen reflow atmosphere, probe technologies - that could assist in improving your soldering process by producing fewer solder defects/ higher yield levels.

  • Next Generation No-Clean Lead Free Solder Paste Evaluation for Fine Pitch Applications
    Fei Xie, Ph.D., Daniel F. Baldwin, Ph.D., Paul N. Houston, and Brian J. Lewis, Engent, Inc.
  • Soldering in Nitrogen Atmosphere - Do Quality Aspects Justify the Costs?
    Speaker of DistinctionChristian Ott, SEHO Systems GmbH; Heike Schlessmann, SEHO North America, Inc.
  • Probe Technologies to Improve First Pass Yields
    Brook Sandy-Smith, Indium Corporation; Brian Crisp, Everett Charles Technologies

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