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Sessions are 1.5 hour programs in which three technical papers are presented under the direction of a chairman. Each paper is presented by the author on a topic related to the main subject of the session, and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers. Organized by track, and by day within each track.
The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.
Please note that speakers with a  icon are recognized as Speakers of Distinction. Over the past 15 years they have been identified by SMTAI attendees as giving the strongest technical presentations. Congratulations to each of these authors for a job exceptionally well done.
MONDAY, OCTOBER 5
8:00am – 9:30am
ET1
Counterfeit Electronics-How to Screen for and to Fight!
Chair: Steve Greathouse, Plexus Corp.
Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Monday, October 5
8:00am–9:30am, California
Counterfeiting is clearly a growing problem in almost all industries, especially electronic products. Almost everyone is being affected by the counterfeiting problem in different ways. Whether you are a parts manufacturer, distributor, individual user, from the government and law enforcement agencies, legal professionals, authentication technology manufacturers, academic institutions, supply chain and brand protection professionals, you are affected. Many suppliers feel that counterfeiting is the number one issue that threatens the electronic supply chain, and corresponding profitability and liability for your products.
This session discusses the issues involved in avoiding, detecting, and preventing counterfeit products, how to screen for, and how to fight this spreading problem. The first paper in the session not only covers the techniques, but states the use of common sense for buyers: "If you get a quote that seems too good to be true, it probably is". The second paper provides a comprehensive review on methods for screening counterfeit electronic parts including use of visual, electrical tests, x-ray, VOM, and decapping. Examples of component authentication are also presented. The last paper comes from authors from the industrial and aerospace sectors providing challenges on detection of counterfeit electronics and how the industry is fighting the problem. Come and learn how to protect yourself and your company from this challenging issue that is consuming industry resources worldwide
Real or Fake? The Counterfeit Chip Conundrum
Dave Loaney, Premier Semiconductor Services
Screening for Counterfeit Electronic Components
Glenn Robertson, Stephen Schoppe, and Fabian Morales, Process Sciences, Inc.
An Industry United to Fight Counterfeiting
Daniel DiMase, Honeywell Technology Solutions Inc. and Phillip Zulueta, Jet Propulsion Laboratory
MONDAY, OCTOBER 5
10:00am – 12:00pm
ET2
Nano Materials and Microwave Cure
Chair: Lars Boettcher, Fraunhofer IZM
Co-Chair: Thomas Loeher, Ph.D., Technical University of Berlin
Monday, October 5
10:00am – 12:00pm, California
Highly reliable and most cost efficient interconnects and surface finishes for IC substrates and PCB are essentially for the increased demands in electronic packaging. Nanotechnology based materials and processes can provide new approaches for the realization of the interconnects. Induced stress into the package by the curing of underfillers does also reduce the reliability and lifetime of electronic products. Conventional curing methods tend to induce high levels of stress into assemblies. A solution here can be the use microwave energy for the curing process. Both topics will be covered in this session and a broad introduction into these emerging technologies will be given.
Adhesion Mechanisms of Nano-Particle Silver Interconnects in Electronics Packaging Applications
Sung Chul Joo and Daniel F. Baldwin, Ph.D., , Georgia Institute of Technology
Nanotechnology for Lead-Free PWB Final Finishes
Nils Arendt, Enthone Inc., a business of Cookson Electronics
Warpage (co-planarity) Reduction for Flip-Chip Underfill Assemblies
Robert Hubbard, Lambda Technologies, Inc.
Unusual Cure Mechanisms of Thermoset Epoxy Resins in Microwave Fields
David Tyler, University of Oregon and Robert Hubbard, Lambda Technologies, Inc.
MONDAY, OCTOBER 5
1:00pm – 2:30pm
ET3
System in Package (SiP)
Chair: Thomas Loeher, Ph.D., Technical University of Berlin
Co-Chair: Irene Sterian, Celestica, Inc.
Monday, October 5
1:00pm – 2:30pm, California
Various technologies for the miniaturization of systems and modules attracted increasing interest for application and gained considerable process maturity during the last years. Depending on the application scenario, the technology of choice can be either advanced chip stacking using silicon through via technology to yield highly miniaturized modules, which can be assembled to a PCB substrate. On the other hand, direct single or multiple chip embedding into the printed circuit board bears the potential for cost effective fabrication of robust modules and substrate boards with very high functional density. Examples of both, silicone stacking and die embedding into PCBs, will be covered in the SiP session.
Wafer Level Packaging Technology Trends for CMOS Image Sensors
Andrew Perkins, Ph.D., Swarnal Borthakur, and Marc Sulfridge, Aptina
Imbedded Die Assembly Process, Is It Ready Yet?
Jim D. Raby, P.E., Mark McMeen, and Casey H. Cooper, STI Electronics, Inc.
Innovative Package Realization by Chip Embedding Technologies
L. Boettcher, S. Karaszkiewicz, and A. Ostmann, Fraunhofer IZM; D. Manessis and H. Reichl, Technical University of Berlin
MONDAY, OCTOBER 5
3:00pm – 5:00pm
ET4
Evolving Technology and Current Issues Panel - FREE Beer and Pretzels!
Chair: Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory
Co-Chair: Andrew Perkins, Ph.D., Aptina
Monday, October 5
3:00pm – 5:00pm, California
Come and join the team of industry experts to learn where the technology is heading and the current key issues in packaging, surface mount materials and manufacturing. Experts from industry will first present an overview of current and future technology, current status of solar and the SMT relationship, as well as a special presentation on Stretchable Electronics. Bring your challenging issues/questions from work to get answers from experts who provide unique perspectives based on their experience.
Panelists will include:
Ken Gilleo, Ph.D., ET-Trends LLC, (The Next Generation)
Thomas Loeher, Ph.D., Technical University of Berlin, (PCB Technologies for the Realization of Stretchable Electronic Systems)
Irene Sterian, Celestica Inc., (Solar Energy and SMT)
Charles Woychik, Ph.D., GE Global Research, (Advanced Packaging)
Steve Greathouse, Plexus Corp., (New/Evolving Technologies)
Lars Boettcher, Fraunhofer IZM, (European Packaging Activity)
TUESDAY, OCTOBER 6
10:00am – 11:30am
AAT1
Advancements in Electronic Packaging
Chair: Andrew Mawer, Freescale Semiconductor
Co-Chair: Pradeep Lall, Ph.D., Auburn University
Tuesday, October 6
10:00am – 11:30m, Golden West
This session will cover some of the latest advancements in various aspects of electronics packaging. The first presentation covers a new type of electrically conductive epoxy die attach for electronic packages that utilizes graphite nano platelets as the filler material, including with gold coating of the platelets. The second paper of the session discusses the use of EMI shielding at the package, instead of the PCB, level. System in a package (SiP), package on package (PoP) and single chip package applications of this technology will be outlined. Finally, the last presentation will detail the complex packaging of a MEMS-based ultrasonic transducer along with four ASIC devices using a single Teflon interposer based flip chip HyperBGA package.
Evaluation of Epoxy Conductive Adhesives Containing Graphite Nano Platelets Fillers
Guilian Gao, Ph.D., Daniel Roitman, Vandana Vijayakumar, and Ken Honer, Tessera Inc., Xiaobo Sun, Palanisamy Ramesh, and Robert C. Haddon, University of California-Riverside
Autosplice Chip Shield™ Technology Revolutionizes SiP (System-in-Package) Wireless Chip Level EMI Shielding Requirements
Fred Grabau, Autosplice, Inc.
Packaging High Density Capacitive Micro-Machined Ultrasonic Transducers (cMUT) Sensor Arrays Using HyperBGA Technology
Charles G. Woychik, Ph.D., Robert Wodnicki, Rayette Fisher, and Kai Thomenius, GE Global Research; Glen Thomas, Irv Memis, Ulises Penaherrera, and Barry Bonitz, Endicott Interconnect Technologies, Inc.
SMT1
Cleaning and Cleanliness Testing Challenges in a Lead-Free World
Chair: Linda Woody, Lockheed Martin
Co-Chair: Jack Reinke, Kyzen Corporation
Tuesday, October 6
10:00am – 11:30am, San Diego
Cleaning challenges are increasing due to the evolution of high density designs and the transition to lead free soldering flux chemistries. Both create separate and additive requirements for cleaning and cleanliness testing. This session will explore cleaning chemistries, flux chemistries, and cleanliness testing chemistries in an effort to provide insight into current technologies and what work is still needed in the area of critical cleaning and cleanliness testing.
Lead-Free Flux Technology and Influence on Cleaning
Ning-Cheng Lee, Ph.D., Indium Corporation
Limitations of DI-Water Cleaning Processes
Harald Wack, Ph.D., and Sinisa Aleksic, Ph.D., ZESTRON America
Ionic Cleanliness Testing Research of Printed Wiring Boards for Purposes of Process Control
Mike BixenmanDBA, Kyzen Corporation; Ning-Cheng Lee, Ph.D.,, Indium Corporation; and Steve Stach, Austin American Corporation
MFX1
Understanding and Reducing the Head in Pillow Component Soldering Defect
Chair: Jasbir Bath, Christopher Associates/Koki Solders
Co-Chair: Chrys Shea, Shea Engineering
Tuesday, October 6
10:00am – 12:00pm, Royal Palms 3-4
Incidences of the Head-in-Pillow component solder defects have increased over the last few years, especially with the movement to lead-free soldering which has increased the potential for component warpage. This defect is not easy to detect with conventional manufacturing inspection tools and can lead to failure in the field. This session will review the factors and causes of the defect such as warpage, contamination, materials, design and component pitch and offer potential solutions to reduce the effect such as alloy, reflow and paste development. Test methods will be presented to assess this defect on a range of components including BGA/CSP, PoP and BGA sockets. Industry standards affecting the reduction of the head-in-pillow component soldering defect will be reviewed, will need to be updated or in some cases developed for component and board co-planarity in the as-received and reflowed conditions.
Head-and-Pillow SMT Failure Modes
Dudi Amir, Wei Wei Chin, Ph.D., Paramjeet Gill, Scott Buttars, and Raiyo Aspandiar, Intel Corporation
Awakening from Head-in-Pillow? A Novel Pre-Production Test Method for BGA Non-Wet
Masato Shimamura, SMIC; Tetsuya Okuno, Satoru Akita, and Derek Daily, Senju Comtek Corporation
Investigation and Development of Tin-lead and Lead-Free Solder Pastes to Reduce the Head-in-Pillow Component Soldering Defect
Jasbir Bath , Christopher Associates/Koki Solders
Head-and-Pillow Defects in BGA Sockets
Dudi Amir, Raiyo Aspandiar, Chonglun Fan, Fay Hua, Bin Li, Gregorio Murtagian, Rajen Sidhu, and Steve Vandervoort, Intel Corporation
TUESDAY, OCTOBER 6
1:30pm – 3:00pm
AAT2
Developments in Package-on-Package Technology
Chair: Lee Smith, Amkor Technology
Co-Chair: Sheldon Schwandt, Research in Motion
Tuesday, October 6
1:30pm – 3:00pm, Golden West
PoP technology has seen strong adoption in mobile multimedia applications the past five years. The first generation of PoP technology, using SMT stacking with flux dip and one pass reflow, has served the industry well despite package warpage challenges. New devices demand thinner, higher density PoP stacks - requiring next generation inspection techniques, dip materials, and bottom package structures that can support finer pitch stacking. This session will cover the SMT assembly and inspection challenges PoP stacking presents and introduce inspection methods, a next generation paste dip material along with SMT assembly and board level reliability results on a new bottom package structure to address current and future PoP challenges.
The Challenges of Package on Package (POP) Devices During Assembly and Inspection
Bob Willis, ASKbobwillis.com and David Bernard, Ph.D., Dage Precision Industries
Next Generation PoP Pastes for Electronics Assembly
Jim Hisert and Brandon Judd, Indium Corporation
Assembly and Reliability Assessment of Fine Pitch TMV Package on Package Components
Heather McCormick, Celestica Inc.; Lee Smith, Jimmy Chow, and Ahmer Syed , Amkor Technology
DCA1
Soldering Bumping
Chair: Don Banks, Banks Solutions
Co-Chair: Lars Boettcher, Fraunhofer IZM
Tuesday, October 6
1:30pm – 3:00pm, Royal Palms 1-2
Even in harsh economic times, implementation of direct chip attach and flip chip technology continues as consumers demand ever-smaller devices. These applications require reliable interconnection through electrically conductive pathways which are typically bumps composed of solder. This session covers recent advances in solder bumping. The first paper presents cost-efficient bumping to process flip chips in a wafer level solder sphere transfer process. The technique uses a patterned vacuum plate to pick up preformed solder spheres, optically inspect for yield, and then transfer them to the wafer. Process parameters for producing 100µm pitch bumps are covered. Next is a review of a roll-to-roll solder bumping process, in which low-temperature Sn-58Bi solder bumps are formed by electroplating on a flexible substrate at a 75µm pitch. Microstructure and mechanical properties of finished solder joints are evaluated including intermetallic compound thickness, shear strength and fracture mode. Last, bumping on the next generation of capacitive micro-machined ultrasonic transducers (cMUTs) is discussed. This is challenging in that the application uses a 275µm thick die with a backside trench cavity. Adequate adhesion to the under bump metallization (UBM) layer and uniform solder bump volume are the focus as process issues encountered in applying solder bumps to a non-planar surface are discussed.
New Solder Bumping Technology and Adapted Assembly Processes for 100 µm Pitch Flip-Chip Technology Using Capillary Flow or No Flow Underfill
Florian Schüßler and Jöerg Franke, Institute FAPS-University of Erlangen-Nuremberg; Rainer Dohle, Micro Systems Engineering GmbH; Thomas Oppert, PAC TECH-Packaging Technologies GmbH; and Georgi Georgiev, KSG Leiterplatten GmbH
Mechanical Properties of Solder Bump Formed on FPCB for Continuous Flip Chip Bonding Process
Sehyung Lee, Yue-Seon Shin, Jun-Ki Kim, and Sehoon Yoo, Korea Institute of Industrial Technology; Chang-Woo Lee, Micro-Joining Center, KITECH
Challenges of Solder Bumping Capacitive Micro-Machined Ultrasonic Transducers (cMUT) Trenched Devices
Charles G. Woychik, Ph.D., Robert Wodnicki, Rayette Fisher, and Kai Thomenius, GE Global Research; Thomas Fritzsch, Oswin Ehrmann, Rafael Jordan, and Veronika Glaw, Fraunhofer IZM
SMT2
Optimizing the Miniature Component Solder Paste Printing Process
Chair: Joe Belmonte, Bose Corporation
Co-Chair: Jeff Kennedy, Celestica, Inc.
Tuesday, October 6
1:30pm – 3:00pm, San Diego
SMT Assembly is going through a challenging phase with the introduction of miniature components such as uBGA's, .3mm CSP's and 01005 passives into the assembly process. Example assemblies are cell phones and other hand held devices driven by consumer demand for smaller devices with increased functionality. Printing these miniature devices along with more conventional SMT devices like .5mm QFP's and 0603 and 0805 passives is a challenge.
How much miniaturization is possible before there is a paradigm shift in the technology? At what point is solder paste no longer useful? How small of a feature can be printed with solder paste and can this process be implemented into a production environment? Most of the factors and critical parameters in ultra-fine pitch printing are well understood and documented for over twenty years. Some of the known critical parameters to obtain an acceptable solder paste deposit (or paste transfer efficiency) are squeegee speed, squeegee pressure, stencil design (technology, thickness & area ratio) and solder paste. But as the pitch and aperture sizes get smaller and smaller for printing onto the circuit board, we begin to see additional factors have effect on the solder paste deposition (transfer efficiency). What are these factors and can these factors be controlled in order to obtain acceptable results for transfer efficiency and minimized variability? This session will examine several approaches to resolve this issue.
Sustaining a Robust Fine Feature Printing Process
Richard Brooks, Christopher Associates; George Babka, Assembléon Americas; David Sbiroli and Chris Anglin, Indium Corporation
Stencil Considerations for Miniature Components
William E. Coleman, Ph.D., and Cory Holda, Photo Stencil
Stencil Design Guidelines for Robust Printing Processes in Electronics Production Considering Stencil and Solder Paste Specific Properties
Michael Roesch and Jöerg Franke, Institute FAPS-University of Erlangen-Nuremberg
MFX2
Alternate Lead-Free Alloys
Chair: Ron Lasky, Ph.D., Dartmouth College/Indium Corporation
Co-Chair: Mumtaz Bora, Peregrine Semiconductor
Tuesday, October 6
1:30pm – 3:00pm, Royal Palms 3-4
The advent of lead-free soldering with the de-facto SAC305 standard and its close relatives has resulted in poor performance and increased cost in some applications. It is only natural that research for substitute materials would transpire. This session will cover some of the work in this arena, most notably Investigations on the processability of SnCuNi alloy for SMT assembly, efforts to minimize and standardize the number of lead-free alloys used, and experimental data and its interpretation for some "second generation" lead-free alloys. The papers will present process development, reliability data, and explanation of the results. This session is ideal for the person who wants to be brought up to speed on what is happening in alternative lead-free alloys to improve performance and reduce cost.
Characterizing Alternative Alloys for SMT Assembly
Denis Barbini, Ph.D., and Ursula Marquez de Tino, Ph.D., Vitronics Soltec; Brian Roggeman, UNOVIS Solutions
The Proliferation of Lead-Free Alloys
Timothy Jensen and Eric Bastow, Indium Corporation
Second Generation Lead-Free Alloys
Randy Schueller, Ph. D., and Joelle Arnold, DfR Solutions
RoHS1
Meeting the Demands of RoHS and REACH Compliance
Chair: Rob Rowland, RadiSys Corporation
Co-Chair: Scott Penin, Paradigm Contract Manufacturing
Tuesday, October 6
1:30pm – 3:00pm, Royal Palms 5-6
Achieving RoHS (Restriction of Hazardous Substances) compliance was a major accomplishment; however this was only the beginning. RoHS is spreading and it has become a global phenomena and REACH (Registration, Evaluation, Authorization and Restriction of Chemicals) legislation became a reality in 2008. What's next regarding RoHS and REACH legislation and how will it impact you? This session will cover data collection options that companies can deploy in connection with suppliers and customers to comply with RoHS and REACH requirements; the current state of RoHS exemptions and how to create and deploy an exemption transition strategy that can be applied to the phase out of exemptions; and how to convert products, the supply chain and data systems to meet current and future RoHS regulations throughout a product's life cycle.
RoHS vs. REACH, What Does This Mean to IT Hardware Companies and Data Management?
Jacklin Adams, Louis Ferretti, Fabio White, and Darren Samson, IBM Corporation
European Union RoHS Exemption Review Case Study
Marie Cole, Jacklin Adams, Steve Bushnell, George Galyon, Ph.D., Curtis Grosskopf, Mark Hoffmeyer, and Jim Wilcox, IBM Corporation
RoHS-Changing Products to Conform With the New European Union RoHS Regulations
George Galyon, Ph.D., Marie Cole, Jacklin Adams, John Quick, Fabio White, Lou Ferretti, and Sophia Lau, IBM Corporation
TUESDAY, OCTOBER 6
3:30pm – 5:00pm
AAT3
Drop/Shock/Bend Reliability
Chair: Ahmer Syed, Amkor Technology, Inc.
Co-Chair: Andrew Mawer, Freescale Semiconductor
Tuesday, October 6
3:30pm – 5:00pm, Golden West
The requirement for enhancing solder interconnect reliability under drop, shock, and bend conditions continues to drive the development of new materials and better prediction tools. The first two papers in this session deal with experimental data on Pb free solder alloy composition and underfill coverage effect on board level reliability. The final paper presents a methodology for life prediction for Pb free solder alloys for drop/shock conditions.
Board Level Reliability Comparison of Lead-Free Alloys
Robert Darveaux, Ph.D., Corey Reichman, Sabira Enayet, Wen-Sung Hsu, and Win Thandar Swe, Amkor Technology
Thermal Cycle and Drop Reliability of Lead-Free Assemblies With No-and Corner-Underfill
Bankeem Chheda and S. Manian Ramkumar, Ph.D., CEMA, Rochester Institute of Technology; Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Models for Prediction of Shock Reliability for Lead-Free Area-Array Components in Portable Electronics
Pradeep Lall, Ph.D., Sandeep Shantaram, Ph.D., Mandar Kulkarni, Arjun Angral, and Dhananjay Panchagade, Auburn University-Department of Mechanical Engineering and Center for Advanced Vehicle Electronics
DCA2
Underfills and Pad Metallizations for Flip Chip and CSP Applications
Chair: Charles Woychik, Ph.D., GE Global Research
Co-Chair: Don Banks, Banks Consulting
Tuesday, October 6
3:30pm – 5:00pm, Royal Palms 1-2
Two important process areas for fine pitch area array solder attach continue to focus on improvements of the underfill process and pad metallizations that are compatible with Pb-free solders to ensure a robust solder interconnect. Particular attention continues to focus on developing a robust underfill process for no-flow materials. Typically this class of underfills has been used for low I/O devices with mild reliability requirements. In this session, a new process will be discussed for a high-end flip chip application having over 3000 I/O pads with 150um pitch. A nearly void free assembly process has been achieved using commercially available no-flow underfill materials. In addition, different CSP package sizes respond differently to today's underfill systems. Likewise, diverse underfill technologies offer varying levels of reliability depending on package size or type. To understand these dynamics, a study was conducted to evaluate underfill system reliability capabilities and performance as they relate to different CSP package sizes. Data presented will include thermal cycling reliability, drop test performance and failure mode analysis for CSPs used in commercial applications such as handheld products and mobile computing devices. Another challenge with fine pitch solder assembly is having a solderable pad to mate with the Pb-free bumped die, such that a reliable solder interconnect is formed. Different types of Ni-Au plating processes will be discussed to ensure that a Pb-free solder bump can produce a reliable interconnect, especially for WLCSP applications. Attend this session on fine pitch solder assembly processes to learn more how process parameters, and materials can produce high yield interconnects with maximum fatigue life.
No-Flow Underfill Voids Nucleation Study in High, Stable Yield, and Near Void-Free Assembly Process Development
Sangil Lee and Daniel F. Baldwin, Ph.D., Georgia Institute of Technology
Effect of Package Sizes and Underfill on CSP Reliability
Brian J. Toleno, Ph.D., and Tom White, Henkel Corporation
A Comparison of Electroless and Electroplated Ni/Au UBM Structures for Board Level Reliability of WLCSP Devices
Luke England, Fairchild Semiconductor
SMT3
Optimizing the Solder Paste Printing Process for Assemblies with Standard and Miniature Components (Broadband Printing)
Chair: Joe Belmonte, Bose Corporation
Co-Chair: Tim Jensen, Indium Corporation
Tuesday, October 6
3:30pm – 5:00pm, San Diego
Designing products with decreasing feature size and increasing complexity is not an impasse nor is producing products that have larger components; the dilemma is when both are required on the same product. Optimizing the solder paste printing process to accommodate a "mixed technology" product is an ever increasing challenge. One term used for this "mixed technology printing" challenge is "Broadband Printing". Broadband Printing is defined, as the printing process that must satisfy the solder paste volume requirements for a PCB with both miniature and larger components existing side by side. This creates a fundamental challenge in satisfying the solder paste need for both small and large components. Clearly, there is no one approach that has surfaced as the ultimate solution. Hence, research continues in this area to gain knowledge and empower board assembler to arrive at the most cost effective solution. This session will examine several approaches to optimize the "Broadband Printing Process".
Optimising the Print Process for Mixed Technology – A Design of Experiment Approach
Clive Ashmore, DEK Printing Machines
Advance In Broadband Printing
Rita Mohanty, Ph.D., Speedline Technologies, and Rick Love, Cookson Electronics Assembly Materials–Engineered Products
iNEMI Solder Paste Deposition Project - Step Stencil Printing Study 
Shoukai Zhang and Laye Feng, Huawei Technology; Xiaodong Jiang, Alcatel-Lucent Shanghai Bell; Rita Mohanty, Ph.D., Speedline Technologies, Inc.; Runsheng Mao, Ph.D.; Indium Corporation, Chuan Xia, Cisco Systems (HK) Ltd.; Desmond Teoh, Celestica Inc.; Jim Arnold, Ph.D., and Haley Fu, Ph.D., iNEMI
MFX3
Connector Technology
Chair: Jim Zanolli, TEKA Interconnection Systems
Co-Chair: Heather McCormick, Celestica, Inc.
Tuesday, October 6
3:30pm – 5:00pm, Royal Palms 3-4
Increasing customer requirements for performance, density, and reliability are creating challenges for SMT area array and thru-hole connectors. These challenges span all aspects from design to manufacturing and rework. This session will address SMT area array design considerations, connector solder attachment methods and thru-hole connector rework technologies.
Assessing Design Tradeoffs with a Customizable Area-Array Connector
Woody Maynard, John Williams, Dinesh Kalakkad, Ken Matsubayashi, and Paul Chen, Neoconix, Inc.
Solder Charge SMT: Design and Validation of New Solder Attach Technologies
Adam Stanczak, Kirk Peloza, and James Hines, Molex, Inc.; David Geiger and Dennis Willie, Flextronics International
Thru Hole Connector Rework Using Convection Heating
Mark J. Walz, et al., VJ Electronix, Inc.
ROHS2
Addressing Tin Whisker Concerns
Chair: Rob Rowland, RadiSys Corporation
Co-Chair: Scott Penin, Paradigm Contract Manufacturing
Tuesday, October 6
3:30pm – 5:00pm, Palms 5-6
The transition to Pb-free surface finishes continues to cause anxiety because of ongoing concerns about tin whisker growth and the potential impact to product reliability. Tin whiskers are a metallurgical phenomenon associated with tin rich or pure tin finishes. The exact cause of tin whisker growth is still a mystery, but it appears to be related to compressive stress levels within the tin. The variables that cause tin whisker growth are not well understood and there has been a lack of analytical tools and standardized test methods. Industry research continues to investigate this phenomenon in an effort to minimize the impact of tin whiskers. This session will cover the mis-identification of tin/copper intermetallic structures as tin whiskers; quantitative methods for identifying tin whisker growth, and the risk of tin whisker growth on tin coated wires and cables.
False Tin Whiskers: Masquerading Tin Copper Intermetallics
David Hillman, Rockwell Collins
Investigating the Mechanism of Tin Whisker Growth Using Quantitative Method
Jing Cheng and James C. M. Li, University of Rochester; Paul T. Vianco, Ph.D.,, Sandia National Laboratories
Assessment of Whisker Growth From Tin Plated Wire and Cable
Thomas Lesniewski, Northrop Grumman
WEDNESDAY, OCTOBER 7
8:00am – 9:30am
AAT4
Characterization of BGA Reliability
Chair: Hugh Roberts., Atotech
Co-Chair: Irene Sterian, Celestica, Inc.
Wednesday, October 7
8:00am – 9:30am, Golden West
The transition to lead-free solder alloys has prompted concerns regarding the reliability of BGA interconnects to withstand both mechanically and thermally induced stresses. The continuing miniaturization of both package and board interconnects also contributes to these concerns, essentially creating a "moving target" in terms of performance requirements. Increased speed-to-market and continuing cost reductions place further demands on such reliability assessments. Three very separate but related reliability topics are presented in this session, addressing correlation of different reliability testing methodologies, examination of package-level and board-level stress from thermally induced warpage and compatibility improvement for lead-free components with tin-lead assembly techniques.
Effect of Structural Design Parameters on Ball Shear Testing Reliability and Their Effect on Determining Acceleration Factors on Accelerated Thermal Cycling
Dereje Agonafer and Nikhil Lakhakar, University of Texas at Arlington
Thermo-Mechanical Simulation and Optimization Analysis for Warpage-Induced PBGA Solder Joint Failure
Caiying He, Ph.D., Zuyao Liu, Hongxia Wang, Feng Lu, Ph.D., Lei Wang and Hongfeng Ran, Shenzhen Kaifa Technology Co., Ltd.
Reliability Assessment of Reballed PBGAs
J. Li, S. Poranki, and K. Srihari, Ph.D.; Watson Institute for Systems Excellence- State University of New York at Binghamton; M. Abtew and R. Kinyanjui, Ph.D., Sanmina-SCI Corporation
SMT4
Challenges and Solutions Relating to the Rework of QFN (Quad Flat No-Lead) Packages
Chair: Craig Hamilton, Celestica Inc.
Co-Chair: Matt Kelly, IBM Corporation
Wednesday, October 7
8:00am – 9:30am, San Diego
The QFN or Quad Flat No Lead is similar to the Quad Flat Package (QFP), but the leads do not extend out from the sides of the package. The perimeter lands are located on the bottom of the package providing the electrical connection. Another unique characteristic is the existence of a center thermal pad, which provides an efficient heat transfer path when soldered to the PCB, helping to increase the thermal performance of the part. This package type was introduced specifically for applications where size, weight, thermal and electrical performance are important. The QFN however, does offer some technical challenges specifically in a lead-free environment, due to its unique structure and low stand-off. This session will highlight some of these challenges specifically relating to the rework process and post rework cleaning of this unique package type.
Fine-Pitch QFN Rework - Triple the Challenge in a Lead-Free World
Neil O'Brien, Finetech Inc.
Cleaning for Reliability Post QFN Rework
Mike Bixenman, DBA, Kyzen Corporation
Reworking the Latest High Technical Challenging SMT Packages - Fusion Quad Pack
Paul Wood, OK International/Metcal and Bill Rugg, Seagate Technology
MFX4
Optimizing Electronic Manufacturing: Do or Die
Chair: Denis Barbini, Ph.D., Vitronics Soltec
Co-Chair: Jasbir Bath, Christopher Associates
Wednesday, October 7
8:00am – 9:30am, Royal Palms 5-6
To remain competitive in today's manufacturing market, a company must implement a clear strategy that focuses on the market needs while leveraging that company's strengths and assets. Implementing best practices is a mixture of leadership, people, systems, and process controls. This session will take the sum of these parts to make a complete picture for the attendee.
Alternative Assembly Options to Achieve Cost Effective and Reliable Handheld Products
Jonas Sjoberg and Andreas Morr, Flextronics Mobile Consumer
Rapid Company Transformation: Lessons Learned in Real Time
John Walsh, Sypris Electronics, LLC
Work Flow Balancing in a Shop Floor Using Petrinets
S.K. Vinod Das, MTS, and P. Gopalakrishnan, HCL Technologies Limited
PRC1
Using Automated Inspection to Reduce Cost Through Process Capability and Control
Chair: Tom Borkes, The Jefferson Project
Co-Chair: Michelle Ogihara, Seika Machinery
Wednesday, October 7
8:00am – 9:30am, Royal Palms 1-2
Having capable and controllable assembly processes are essential elements that characterize successful electronic manufacturing companies. Why? High production yields result in low labor and scrap costs.
An assembly infrastructure that takes advantage of today's automated inspection technologies assists in the goal of achieving best-in-class yields, as well as, significantly reducing the labor costs associated with manual inspection. The key to process control is not to use these automated inspection tools reactively, but to use them proactively in real time – identifying a process trending toward an upper or lower spec. limit, not waiting until a process goes out of control.
Micro packages such a 0201 and 01005s, lead free solder, BGAs and other under-package I/O components have all confounded the inspection challenge. The three papers in this session will document work that has been done to help meet these challenges.
Controlling the Assembly Process With the Use of SPC
William Beair, Raytheon Systems Company
Automatic Solder Paste Printer Positional Feedback Control
Paul Haugen, Cyber Optics Corporation and Rita Mohanty, Ph.D., Speedline Technologies
Improving Inspection of Lead-Free Solder
Christian Munoz, Hirox Corporation
SUB1
New Technical Advancements in PCB Surface Finishes
Chair: Randy Schueller, Ph.D., DfR Solutions
Co-Chair: Michael Carano, OMG Electronic Chemicals
Wednesday, October 7
8:00am – 9:30am, Royal Palms 3-4
The surface finish one selects for the PCB is oftentimes the most critical decision in enabling a successful assembly process, and ultimately a reliable end product. The fact that there are half a dozen widely used surface finishes currently on the market suggests there is no single one that meets the many needs of the industry and thus sacrifices are being made. Much research and development is taking place to significantly improve existing surface finishes and in some cases invent new finishes with attributes suitable for a wider range of products. This session contains three excellent papers; the first addresses the important issue of controlling creep corrosion failure on immersion silver PCBs. The new use of organic metals to greatly improve the characteristics of immersion tin finishes is presented in the second paper. The final paper is the revealing of a promising new surface finish material with many attractive properties for the electronics industry. Anyone involved in design, assembly, or reliability would benefit from this session.
An Immersion Silver PWB Surface Finish to Combat Harsh Environments
Ernest Long, Ph.D., Lenora Toscano, and John Swanson, MacDermid, Inc.
Thin Immersion Tin Using Organic Metals
James Kenny, Nils Arendt, Bernhard Wessling, Karl Wengenroth, Yung Herng Yau, Ph.D., and Holger Merkle, Enthone Inc., a business of Cookson Electronics
A New Breakthrough PCB Surface Finish
Frank Ferdinandi, Crombie 123 Ltd.; Rod Smith, Ph.D., and Mark Humphries, Ph.D.,
PA Consulting
WEDNESDAY, OCTOBER 7
10:00am – 11:30am
AAT5
BGA Reliability: Process, Materials and Cycling Variations
Chair: Marie Cole, IBM Corporation
Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Wednesday, October 7
10:00am – 11:30m, Golden West
Although Pb-free BGAs have been used extensively since 2006, there is still significant learning needed to understand many aspects of their solder joint reliability, especially while the industry is in a state of transition. And during this transition phase, there continues to be reball requirements to maintain traditional SnPb processes. In addition, new Pb-free alloys have been introduced to address issues such as mechanical fragility. How do these low silver alloys perform when mixed with standard Pb-free SAC and/or traditional SnPb? What process parameters contribute to the solder joint thermal fatigue life of reballed BGAs and low silver Pb-free BGAs? Does power cycling offer a more realistic representation of field conditions for lab reliability testing? Attend this BGA reliability session to learn more about how process parameters, material changes and cycling conditions can affect BGA solder joint fatigue life.
Assessing Reliability of Reballed Ball Grid Array Assemblies Under Temperature Cycling Test
Lei Nie, CALCE-University of Maryland
Low Silver BGA Assembly Phase I-Reflow Considerations and Joint Homogeneity Fourth Report: Sensitivity to Process Variations
Chrys Shea, Shea Engineering Services; Ken Hubbard and Gnyaneshwar Ramakrishna, Cisco Systems; Ahmer Syed, Amkor Technology; Greg Henshall, Ph.D., Hewlett-Packard; Ranjit Pandher, Cookson Electronics; Quyen Chu and Girish Wable, Jabil Circuit, Inc.
Comparisons of SAC Flip Chip BGA Solder Joint Reliability Under Accelerated Temperature Cycling and Power Cycling Conditions
Ron Zhang, Chirag Shah, and Stanley Pecavar, Sun Microsystems
SMT5
Process and Design Optimization for Selective Soldering
Chair: Dan Baldwin, Ph.D., Engent, Inc.
Co-Chair: Denis Jean, Plexus
Wednesday, October 7
10:00am – 11:30am, San Diego
Selective soldering has been widely implemented in recent years. As with all new process technologies, there has been a significant learning curve during its implementation ramp. This session highlights key process optimization results, design for manufacturing guidelines and techniques, and best process practices for transitioning from low to high temperature solders.
Optimizing the Selective Soldering Process
Denis Barbini, Ph.D., and Ursula Marquez de Tino, Ph.D., Vitronics Soltec
Effects of an Appropriate PCB Layout and Soldering Nozzle Design on Quality and Cost Structure in Selective Soldering Processes
Christian Ott, SEHO Systems GmbH
Selective Soldering with High Temp Alloys
Ernie Grice, ERSA
MFX5
Delving Into Discretes
Chair: Irene Sterian, Celestica Inc.
Co-Chair: Rich Freiberger, ZF Array Technology
Wednesday, October 7
10:00am – 11:00am, Royal Palms 5-6
The use of SMT discrete components is prevalent today in many different ttypes of assemblies. This session will look at some of the issues associated with current discrete components, in particular driven by miniaturization and cost reduction pressures. The focus on miniaturization has driven components from 0402 to 0201 to 01005 sizes. These 01005
components, the thickness of a hair, need new stencil, paste, and pad optimization work to be completed, before they can achieve the same yield and robust assembly process as the more conventional 0402 and 0201 components. The focus on cost reduction has pushed manufacturing to low cost labour regions, and has resurfaced an old defect: tombstoning. This has recently been observed in low cost MLC (multi layer ceramic) capacitors. Fortunately there are tests available that can screen for this condition prior to assembly. If you would like to better understand the issues around discrete components in today's industry, join us for this session.
Design and Process Development for the Assembly of 01005 Passive Components
J. Li, S. Poranki, and K. Srihari, Ph.D., State University of New York at Binghamton; R. Gallardo, M. Abtew, and R. Kinyanjui, Ph.D., Sanmina-SCI Corporation
Tombstone Capacitors Revisited, Now Do We Need a PSL (Plating Sensitivity Level) Specification for Chip Components
John Maxwell and Chris England, Johanson Dielectrics, Inc
PRC2
Failure Analysis
Chair: Brian Toleno, Ph.D., Henkel Technology
Co-Chair: Salvatore Rampaul-Pino, Vision Research, an AMTEK Company
Wednesday, October 7
10:00am – 11:30am, Royal Palms 1-2
Determining and detecting failures in complex electronics devices in order to minimize field failures. In this session we look at a combination of modeling, non-destructive, and destructive analysis to analyze and predict failures. In the first paper fracture mechanics of BGA solder joints are modeled based on empirical data so that the effects of surface finish can be better understood. In the second paper contamination analysis is examined utilizing X-ray fluorescence methodology. Finally, a combination of non-destructive and destructive analysis are used in order to determine the optimum process conditions in order to produce reliable soldered QFN devices.
Proposal for Using FA Fracture Mechanics Approach to Solder Reliability
Dick Casali, Intel Corporation
Micro-Particle and Contaminant Analysis Using XRF With State-of-Art Mapping
Jun Choi and Robert Johnson, SII NanoTechnology USA
How to Resolve Defects Related to Pad Design With the Aid of Non-Destructive (X-Ray, SPI) and Destructive Methods (Cross Section, Shear Test)
Zhen (Jane) Feng, Ph.D., Hung Le, Roy Chung, Raymond Tran, Sati Johal, and Murad Kurwa, Flextronics International
SUB2
Advanced Surface Finishes for Lead-Free Applications
Chair: Jim Kenny, Enthone Inc., a business of Cookson Electronics
Co-Chair: Raiyo Aspandiar, Intel Corporation
Wednesday, October 7
10:00am – 11:30am, Royal Palms 3-4
This session reviews updated information regarding the use of immersion tin and electroless nickel, electroless palladium, immersion or electroless gold processes for lead-free applications. Additionally reliability data will be presented on the effects of OSP, Immersion Silver and ENIG surface finishes on assemblies.
The Development and Implementation of an Improved Immersion Tin Plating Process Tin-Lead and Lead-Free Soldering
Hank Lajoie, OMG Electronic Chemicals
Electroless Ni/Electroless Pd/Immersion Au/Electroless Au (ENEPIGEG) Plating Process for Gold Wire Bonding on Organic Package Substrate
Kiyoshi Hasegawa, Yoshinori Ejiri, Takehisa Sakurai, and Yoshiaki Tubomatsu, Hitachi Chemical Co., Ltd.
Surface Finish Effect on Reliability of Lead Free Electronic Assemblies
Maurice N. Collins, Ph.D., Michael Reid, and Jeff Punch, Stokes Institute-University of Limerick; Richard Coyle, Ph.D., Alcatel-Lucent
WEDNESDAY, OCTOBER 7
1:30pm – 3:00pm
AAT6
Problems and Promises of BTCs: Bottom Termination Components
Chair: Ray Prasad, Ray Prasad Consultancy
Co-Chair: Andrew Mawer, Freescale Semiconductor
Wednesday, October 7
1:30pm – 3:00pm, Golden West
You may not know the term "BTC" but expect to hear more and more about them in the future. BTC relates to industry descriptive package names such as QFN, DFN, SON, LGA, MLP etc. BTCs provide good electrical and thermal performance and they are very inexpensive packages. But they do require perfection not only in the assembly processes but perfection on the part of the PCB and component suppliers as well. Since perfection is hard to come by, they can pose reliability challenges caused by different package lead configuration and alloy compositions used to solder them.
Following a brief description of industry effort to address BTC Design and Assembly challenges (IPC 7093) co-chaired by Ray Prasad, this session will provide an overview of package manufacturing processes by a speaker involved in day to day manufacturing of this package. The paper will provide details such as the most common package geometries, material systems and manufacturing processes to give you a broad and sound foundation for utilizing QFN packaging for semiconductors. Then we move on to discussion of the reasons for dual row QFNs providing better reliability while also increasing package density. We conclude the session with the last speaker who compares impact of different SAC alloys on QFN solder joint reliability.
QFN Manufacturing: Configurations, Materials and Processes
Richard Otte, Promex Industries Inc.
Solder Joint Reliability Analysis and Testing of a Dual Row QFN Package
Luke England, Yong Liu, and Richard Qian, Fairchild Semiconductor
Thermal Fatigue Performance of a Quad Flat No Lead (QFN) Package Assembled with Several Sn-Ag-Cu (SAC), Pb-free Solders
Richard Coyle, Ph.D., Peter Read, Richard Popowich, and Debra Fleming, Alcatel-Lucent; Heather McCormick, Celestica Inc.
SMT6
Convection vs. Vapor Phase Soldering: Process Optimization, Control, and Reflow Environment Considerations for High Quality, High Reliability Assembly
Chair: Matt Kelly, IBM Corporation
Co-Chair: Randy Schueller, Ph.D., DfR Solutions
Wednesday, October 7
1:30pm – 3:00pm, San Diego
With the ever increasing complexity of today's electronic hardware, process selection and optimization during reflow operations are becoming more difficult. A growing number of considerations continue to emerge when assembling high thermal mass, high complexity assemblies. This session is intended to discuss numerous elements during the reflow process including profile optimization iteration, tin whisker mitigation techniques during reflow, and a comparison between convection versus vapor phase reflow techniques.
Developing the Optimum Reflow Process: A Matter of Cost and Quality
Denis Barbini, Ph.D., Ursula Marquez de Tino, Ph.D., and Jon Silin, Vitronics Soltec
Effects of Reflow Atmosphere and Flux on Sn Whisker Growth of Sn-Ag-Cu Solders
Bryan Stone, Sharon Huang, Benjamin Jurcik, and Shigeyoshi Nozawa, Air Liquide Laboratories; Alongheng Baated, Keun-Soo Kim, and Katsuaki Suganuma, Institute of Scientific and Industrial Research, Osaka University; Minoru Ueshima, Senju Metals Industries, Co. Ltd.
Re-Introduction of Vapor Phase Soldering Technology for Lead-Free Application
Adzahar Samat, Venture Corporation Ltd.
MFX6
Via and Plated Thru Hole Reliability in Lead-Free Assembly
Chair: Pradeep Lall, Ph.D., Auburn University
Co-Chair: Bill Barthel, Plexus
Wednesday, October 7
1:30pam – 3:00pm, Royal Palms 5-6
Plated thru holes and Vias have been used extensively as board-level interconnects. Migration to lead-free poses challenges especially for harsh environments. The session examines the interplay between the reliability of via and plated through hole in lead-free assembly. The first two papers examine the effect of manufacturing process parameters on via and plated through reliability and the third paper presents an alternate interconnect technology.
Does Copper Dissolution Impact Through-Hole Solder Joint Reliability?
Craig Hamilton and Polina Snugovsky, Ph.D., Celestica Toronto; Mario Moreno, Celestica Mexico; Teng Hoon Ng and Juthathip Fangkangwanwong, Celestica Thailand; Matthew Kelly and Marie Cole, IBM Corporation
Via Reliability – A Holistic Process Approach
David Wolf, Timothy A. Estes, and Ronald J. Rhodes, Conductor Analysis Technologies, Inc.
Environmental Challenges to Conventional PTH Metallization - A Time for Change?
David H. Ormerod, Enthone Inc., a business of Cookson Electronics
SUB3
Fine Pitch Package and Halogen-Free Board Substrates
Chair: Raiyo Aspandiar, Intel Corporation
Co-Chair: Lenora Toscano, MacDermid, Incv
Wednesday, October 7
1:30pm – 3:30pm, Royal Palms 3-4
Two current packaging trends are affecting the materials used in substrates. The first trend is the universal push for greener electronic products. This is resulting in Halogenated Flame Retardant (HFR)-Free Laminates are gaining in popularity. But, transitioning from the commonly used HFR-containing laminates, such as FR-4, to HFR-free laminates is fraught with many risks. The HFR-free laminates' electrical, mechanical and thermal properties may vary considerably from that of presently used laminates as well as from one material type to another. The former part of this Session will delve into the key materials, manufacturing and reliability characteristics of HFR-free laminates. The second trend is the need for smaller area array land geometries on package and board substrates. This trend is pushing the limits of solder paste stencil application process, necessitating alternative solder deposition techniques. The latter part of this Session will describe one such solder deposition process for package substrates.
HFR-Free PCB Materials & Signal Integrity Initiatives
John Davignon and Stephen Hall, Intel Corporation
Evaluation of Halogen-Free Laminates Used in Handheld Electronic Device
David Lau and Norman Zhou, University of Waterloo; Laura J. Turbini, Ph.D., and Julie Liu, Research in Motion
The Smaller the Better - Simultaneous Electrolytic Solder Deposition on Both Sides of a Fine-Pitch Package Substrate
Sven Lamprecht, Hugh Roberts, Shozo Nishida, Fumio Aiki, Bernd Roelfs, Ph.D., Steven Kenny, and Kai-Jens Matejat, Atotech
Contract Manufacturing Symposium
Organized by Mike Buetow
UP Media Group/Circuits Assembly Magazine
Sue Mucha, Powell-Mucha Consulting, Inc.
FREE with VIP or Technical Conference Registration!
EMS1
Business Opportunities in Electronics Manufacturing Services
Chair: Mike Buetow, Circuits Assembly Magazine/UPMedia Group
Co-Chair: Rod Howell, Libra Industries
Wednesday, October 7
1:30pm – 3:00pm, Royal Palms 1-2
While EMS companies remain in the "business of making solder joints," they feel a steady pull by customers, potential customers and the lure of additional revenue to leverage their capabilities across other business pursuits. This session looks at some of the areas where EMS companies from a range of tiers have successfully transitioned to other product offerings -- including solar, fuel cell and repair services -- and other geographies.
How Sanmina-SCI Determined Its Alternative Energies Strategy
Sundar Kamath, Ph.D., Sanmina-SCI
Overcoming Repair Depot Challenges
Greg Bannick, Kimball Electronics Group, Medical Product Solutions
Developing a Robust Offshore Program Management Model
Susan Mucha, Powell-Mucha Consulting, Inc.
WEDNESDAY, OCTOBER 7
3:30pm – 5:00pm
AAT7
Use of Predictive Models for Electronic Assembly and Reliability
Chair: Ron Zhang, Sun Microsystems
Co-Chair: Andrew Mawer, Freescale Semiconductor
Wednesday, October 7
3:30pm – 4:30pm, Golden West
Monte Carlo Simulation for Surface Mount Assembly Head and Pillow Defect Prediction
Fay Hua, Ph.D.,, Shijiang He, and Murtagian Gregorio, Intel Corporation
On the Complete Breakdown of Miner's Rule for Lead-Free BGA Joints
Peter Borgesen, Ph.D., L. Yang, and V. Raghavan, State University of New York at Binghamton; B. Roggeman and L. Yin, Unovis Solutions
SMT7
Solder Paste Technology: The Old and the New
Chair: Laura Turbini, Ph.D., Research in Motion
Co-Chair: Keith Sweatman, Nihon Superior
Wednesday, October 7
3:30pm – 5:00pm, San Diego
Solder paste technology faces many challenges due to the higher temperatures required for lead-free soldering, and the increased circuit density and smaller component sizes. Added to this is the push by computer manufacturers to eliminate all chlorine- and bromine-containing materials. In this session, a comparison of halogen-free lead-free vs halogenated lead-free soldering will be discussed. The development of a new no clean, lead-free, halogen-free fluxing system will be presented. In contrast, the introduction of a new tin/lead solder paste brings the "old standard" up-to-date with an analysis of the paste composition, its behavior in printing and the reflow process. All of these insights can be applied to lead-free pastes as well.
Eliminating Halogens in Solder Paste
Mitch Holtzer, Cookson Electronics
Sealing the Gap of Solder Paste Technology in Lead-Free Halogen-Free Era
Yan Liu, Ph.D., Runsheng Mao, Ph.D., Arnab Dasgupta, Ph.D., and Ning-Cheng Lee, Ph.D., Indium Corporation
Cause and Effect: Characterizing the Relationships Between a Solder Paste's Ingredients and Its Performance on the Assembly Line
Frank Murch, Heraeus Materials Technology, LLC
MFX7
Environmental Stress Screening: Burn In and Thermal Cycling
Chair: Mike Nadreau, Henkel Technology
Co-Chair: Rich Freiberger, ZF Array Technology
Wednesday, October 7
3:30pm – 4:30pm, Royal Palms 5-6
Environmental stress screening (ESS) refers to the process of exposing a newly manufactured or repaired product or component (typically electronic) to stresses such as Burn-in and Temperature Cycling in order to force latent defects to manifest themselves by failure during the screening process. The surviving population, upon completion of screening, can be assumed to have a higher reliability than a similar unscreened population.
This session will focus on the affects of such screening tests on components and substrate materials that have different Thermal Coefficients of Expansion and the issues that this may cause in solder joint stress and specific solder alloys. Also covered will be how to reduce these screening tests by consideration of product design and reliability expectations through statistical analysis in an electronics manufacturing environment.
Thermal Fatigue and Failure Analysis of Sn98.5-95.5Ag1.0-4.0Cu0.5
Maurice N. Collins, Ph.D., Michael Reid, and Jeff Punch, University of Limerick; Richard Coyle, Ph.D., Richard Popowich, Peter Read, Debra Fleming, and Indraneel Chatterji, Alcatel-Lucent
Reducing Burn-in Time Considering Product Design and Reliability Expectations Through Statistical Analysis in an Electronics Manufacturing Environment
Rohan Ashar, Pei-Fang Tsai, and Krishnaswami Srihari, Ph.D., State University of New York at Binghamton
EMS2
Addressing EMS Management Challenges in a Changing World
Chair: Sue Mucha, Powell-Mucha Consulting, Inc.
Co-Chair: Chelsey Drysdale, Circuits Assembly Magazine
Wednesday, October 7
3:30pm – 5:00pm, Royal Palms 1-2
FREE with VIP or Technical Conference Registration!
This session looks at three key areas of strategy development in EMS: ensuring efficient linkage in product development, addressing the challenge of counterfeit products, and exploring opportunities to expand into the solar energy market.
Creating a Robust Design Interface
Craig Arcuri, Alta Manufacturing
Brand Protection Beginning at WIP?
James Williams, Ph.D., Polyonics, Inc.
M&A Opportunities in the Solar Energy Market
Chaim Lubin, Lincoln International
THURSDAY, OCTOBER 8
8:00am – 9:30am
Lead-Free Soldering Technology Symposium
Organized by Paul Vianco, Ph.D., Sandia National Laboratories and Matt Kelly, IBM Corporation
FREE With VIP or Technical Conference Registration!
LF1
National Physical Laboratory Report and Update
Chair: Matt Kelly, IBM Corporation
Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
Thursday, October 8
8:00am – 9:30am, Garden Salon 1
Manufacturing high reliability lead-free circuit assemblies is challenging, and understanding the pitfalls and knowing material properties is clearly desirable. This presentation will address a wide range of issues, which include material and processing properties. Examples include: copper dissolution in selective soldering, tin whisker and work at NPL which has developed a special test vehicle that provides a sensitive test to measure the mitigation properties of conformal coatings, substrate reliability of PTH, solder joint reliability measurements will be discussed and the use of mechanical measurements of joint sized solder samples. The controlling factors in the occurrence of tin pest will also be presented.
Implementation and Reliability Issues With Lead-Free Solders
Christopher Hunt, Ph.D., National Physical Laboratory
THURSDAY, OCTOBER 8
10:00am – 11:30am
LF2
Properties of Alternative Pb-Free Solders
Chair: Paul Vianco, Ph.D., Sandia National Laboratories
Co-Chair: Kola Akinade, Ph.D., Cisco Systems
Thursday, October 8
10:00am – 12:00pm, Garden Salon 1
As Pb-free interconnection technology gains an increasing foothold in the electronics industry, performance shortfalls are now being documented for many alloys, which only a few years ago, were the leading candidates for many consumer and high-reliability applications. It is becoming apparent that a "single" replacement for the SnPb eutectic solder may not be feasible for all hardware applications. This session describes the efforts underway within consortia as well as at individual institutions to document the performance characteristics of new Pb-free solder compositions. These studies are providing critical data to the electronics community in order that smart choices can be made as to the most suitable Pb-free solder to be used in particular applications, from consumer desktop products to high-reliability systems operating in harsh service environments.
Pb-Free Alloy Alternatives: Reliability Investigation
Hans-Juergen Albrecht, Siemens AG
iNEMI Lead-Free Alloy Alternatives Project Report: Thermal Fatigue Experiments and Alloy Test Requirements
Gregory Henshall, Ph.D., Hewlett-Packard; Keith Sweatman and Keith Howell, Nihon Superior Co. Ltd.; Joe Smetana and Richard Coyle, Ph.D., Alcatel-Lucent; Rich Parker, Delphi; Steve Tisdale and Fay Hua, Ph.D., Intel Corporation; Weiping Liu, Ph.D., Indium Corporation; Rob Healey and Ranjit Pandher, Cookson Electronics; Derek Daily, Senju Comtek Corporation; Mark Currie, Henkel Technologies
Processing and Reliability of Low-Silver-Alloys
Mathias Nowottnick, University of Rostock
Joint Properties of Sn3.5Ag Solder Balls Contained Carbon Nanotubes
Chang-Woo Lee, Young-Ki Ko, Jung-Hwan Bang, Sehyung Lee, Yun-Ki Sa, Korea Institute of Industrial Technology; Sehoon Yoo, KITECH
THURSDAY, OCTOBER 8
1:00pm – 2:30pm
LF3
Lead-Free Product Design Qualification: Understanding the Complete Material and Process Picture
Chair: Dave Hillman, Rockwell Collins
Co-Chair: Keith Sweatman, Nihon Superior
Thursday, October 8
1:00pm – 2:30pm, Garden Salon 1
The qualification of a lead-free product requires a product design team to understand not only the component selection and material qualification but the interaction of the design materials with the lead-free soldering process. A thorough assessment and understanding of a products components, laminates, process materials and process procedures results in a high yield, rugged product design that meets the customer requirements. This session focuses on the entire materials & process assessment: the impact of lead-free process on printed wiring board laminate, the interaction of process materials on solder joint integrity and the use of product test vehicle (PTV) methodology for lead-free product design assessment.
Conductive Anodic Filament Study: Laminates and Pb-Free Processing
Randal Ternes, Boeing
The Solder Joint Reliability of WLCSP Components Under Influence of Conformal Coating
Jyri Salminen, Ph.D., Nokia Corporation
Lead-Free Assembly and Qualification of a Storage Class PCBA
Matthew Kelly and Tom Truman, IBM Corporation; Adzahar Samat, Eric Goh, SH Tan, Ali Villanueva, MS Tan, and SJ Lee, Venture Corporation, Ltd.
THURSDAY, OCTOBER 8
3:00pm – 5:00pm
LF4
Impact of Thermal Cycling and Aging Conditions on Lead-Free Solder Joint Reliability Assessment
Chair: Jean-Paul Clech, Ph.D., EPSI, Inc.
Co-Chair: Kola Akinade, Ph.D., Scientific Atlanta, A Cisco Company
Thursday, October 8
3:00pm – 5:00pm, Garden Salon 1
The choice of thermal cycling conditions has a significant impact on accelerated test results, their interpretation and, ultimately, on the assessment of lead-free product solder joint reliability. Presenters in this session feed the debate on appropriate test conditions for lead-free assemblies with hard data and analysis. Test and modeling results are presented that are of use to quantify the effect of temperature extremes, dwell times, and aging conditions on the attachment reliability of both SnPb and lead-free assemblies.
The first paper investigates the performance of lead-free and SnPb assemblies under milder conditions (-20 to 80C) than in conventional accelerated testing. The next two papers provide quantitative insight in the sizable effect of dwell times on accelerated thermal cycling results, including the effect of pre-conditioning (aging), for both SnPb and SAC assemblies. The last paper presents a closed-form, strain-energy based, acceleration factor model that correlates solder joint failure times under a variety of harsh and mild conditions with different cold and hot dwell periods. The proposed framework to develop acceleration factor models is applied to SnPb and SAC305 assemblies.
JCAA/JG-PP Lead-Free Solder Project: -20°C to +80°C Thermal Cycle Test
Thomas Woodrow, Ph.D., Boeing
Effect of Dwell Time on the Life of Lead-Free BGA Joints in Thermal Cycling
P. Borgesen and E. Al-Momani, State University of New York at Binghamton; M. Meilunas, Unovis Solutions
Dwell Time, Microstructural Dependencies, and the Interpretation of Thermal Fatigue Test Data of SnPb and Pb Free Solders
Richard Coyle, Ph.D., Peter Read, Debra Fleming, and Richard Popowich, Alcatel-Lucent; John Osenbach, Jeff Punch, and Maurice Collins, Stokes Institute-University of Limerick; Michael Reid, LSI, Corporation; Heather McCormick, Celestica Inc.; Steven Kummerl, Texas Instruments; and Indraneel Chatterji, Flextronics International
Closed-Form, Strain-Energy Based Acceleration Factors for Thermal Cycling of Lead-Free Assemblies
Jean-Paul Clech, Ph.D., EPSI, Inc.; Greg Henshall, Ph.D., and Jian Miremadi, Hewlett-Packard
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