August 17 - 21, 2008
Disney's Coronado Springs Resort
Orlando, Florida
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Sessions are 1.5 hour programs in which three technical papers are presented under the direction of a chairman. Each paper is presented by the author on a topic related to the main subject of the session, and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers. Organized by track, and by day within each track.
The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.
MONDAY, AUGUST 18
8:00am – 9:30am
ET1
University Research: New Processing for Electronic Packaging
Chair: Lars Boettcher, Fraunhofer IZM
Co-Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Monday, August 18
8:00am – 9:30am
Increasing demands in electronic packaging call for the further development of existing packaging methods and encourage the use of new manufacturing processes. Ink jet printing allows new opportunities for system assembly and integration. This technology can realize structure sizes down to 20 µm line, which is in many cases sufficient for IC contacts and PCB. The use of nano particle inks for such printing processes requires a suitable sintering process. An optimized sintering process is essential for the final properties of ink jet printed circuits. For optoelectronic packaging based on a multi-chip module (MCM), the thermal management becomes crucial. The comprehension of the thermal behavior of the system, by analyzing it with extensive simulations, helps to optimize the package design. The goal is to enable the implementation of an integrated adaptive temperature control for system.
Applicability of Inkjet Technology for Electronics Manufacturing
Kimmo Kaija, Matti Mäntysalo, and Pauliina Mansikkamäki, Tampere University of Technology
Thermal-Analysis of a Silicon-Platform-Based Optoelectronic Multi-Chip Module
Jun Tian and M. Bartek, Delft University of Technology
Sintering of Ag Nano Particle Inks for Printed Electronics
Jussi Pekkanen, Matti Mäntysalo, and Pauliina Mansikkamäki, Tampere University of Technology
FCS1
Alternative Energy: Fuel Cells and Solar Cells Enter High Volume Manufacturing
Chair: Irene Sterian, Celestica Inc.
Co-Chair: Rod Howell, Libra Industries
Monday, August 18
8:00am – 9:30am
Mass Imaging for Alternative Energies
Clive Ashmore, DEK Printing Machines
Solar Material Science at Indium Corporation
David Preische and Fehzan Sayed, Indium Corporation
Screens for Solar Cell Printing
William E. Coleman, Photo Stencil
MONDAY, AUGUST 18
10:00am – 11:30am
ET2
Time for Paradigm Shifts
Chair: Ken Gilleo, Ph.D., ET-Trends LLC
Co-Chair: Steve Greathouse, Plexus Corporation
Monday, August 18
10:00am – 11:30am
All technologies run out of "steam". Knowing when to jump to a future tech is the key to paradigm shift success. We'll cover areas that are ready to shift or stall. We'll start with ESD - an under valuated, but $90-billion problem. A bolder tactic is needed - and it’s ready. Next, it's on to camera modules for mobiles that must keep shrinking in size and cost to thrive - but now is the time to make the jump to WLP. Then, it's on to a new semiconductor transfer printing technique - a massively parallel process for efficiently moving ICs to substrates, especially flexible - and it's ready. Don't hesitate to join us now - it's shift or stall.
Electrostatic Discharge (ESD) and the Technology Roadmap To 2020 and Packaging Performance for Today and the Future
Hartmut Berndt, B.E.STAT European ESD
The Future of Cameras for Mobile Electronics
Yehudit Dagan, Tessera, Inc.
Transfer Printing: An Emerging Technology for Massively Parallel Assembly of Microcircuits
Christopher Bower, Etienne Menard, and Phillip Garrou, Semprius, Inc.
FCS2
Alternative Energy: Fuel Cells and Solar Cells Enter High Volume Manufacturing - Continued
Chair: Irene Sterian, Celestica Inc.
Co-Chair: Emmanuel Siméus, Raytheon Missile Systems
Monday, August 18
10:00am – 11:30am
Design of an Automated Fuel Cell Manufacturing Line
Alexander Proracki and Michael W. Fowler, University of Waterloo
Solar is Hot for Electronics Suppliers
Rob DiMatteo, BTU International
An Alternative Dispense Process for Application of Catalyst Film on MEA's
Horatio Quinones, Ph.D., and Brian Sawatzky, Asymtek
MONDAY, AUGUST 18
11:30am – 1:00pm
Evolving Technologies Keynote Lunch
Solderless Assembly of Electronics – Technical Pipe Dream or Wave of the Future?
Joseph Fjelstad, Verdant Electronics
Monday, August 18
11:30am – 1:00pm
Light lunch served
NOTE: You must pre-register for this symposium to receive lunch.
Solder has been used for the assembly of electronic components to printed circuit boards since the earliest days of the industry; however, it has not been without its problems. Most manufacturing defects are related to soldering and most reliability problems stem from weaknesses in the basic process. Moreover, with the implementation of RoHS and lead-free solder, those problems have been magnified. What if electronic assembly could be accomplished without solder? This is the primary objective of a growing family of related solderless assembly methods that have come be know as Occam Process technologies, in honor of the 14th century philosopher who stressed simplicity. These process approaches are fundamentally reverse order electronics assembly concepts that step away from conventional methods. The technologies now being investigated in locals around the globe obviate the widespread need for and dependence on solder with all of its intrinsic and inherent problems, both legislative and technical. This talk will describe the process, some of its prospective variations, and its prospective benefits that could pave the way for less costly, more environmentally responsible, higher performing, and more reliable electronics assemblies.
Alternative Energy Keynote Lunch
Photovoltaics - The Next Great Electronics Market
A Survey of Opportunities Throughout the Photovoltaics Supply Chain
Jeff Doubrava, Prismark Partners
Monday, August 18
11:45am – 12:30pm
Light lunch served
NOTE: You must pre-register for this symposium to receive lunch.
MONDAY, AUGUST 18
1:00pm – 3:00pm
ET3
Embedded Technologies: Their Applications and Reliability
Chair: Steve Greathouse, Plexus Corporation
Co-Chair: Ken Gilleo, Ph.D., ET-Trends LLC
Monday, August 18
1:00pm – 3:00pm
Embedded technologies have been driven by the need to save board area and/or reduce board size, increase functionality, lower costs and improve electrical performance. Innovative packaging techniques are required in order to meet the increasing size, weight, power, and reliability requirements of this industry without sacrificing electrical, mechanical, or thermal performance. Embedding capacitive layers inside the Printed Circuit Board (PCB) have demonstrated the ability to reduce the number of chip capacitors on the PCB surface as well as greatly improve the performance of the power distribution system. Many systems are being designed to utilize this technology. Learn how this technology is being done, the details behind the problems encountered, and how they are being addressed.
Embedded Chip Packages – Technology and Applications
L. Boettcher and A. Ostmann, Fraunhofer IZM; D. Manessis and H. Reichl, Technical University of Berlin
Advanced Packaging Technologies: Imbedding Components for Increased Reliability
Casey Cooper, STI Electronics, Inc.
Use of Buried Capacitance Layers: Performance and Lessons from A Real World Example
John Andresakis, Oak-Mitsui
Reliability Testing of Advanced Semiconductors Using Embedded Chip Build-Up (ECBU) Packaging Technology
Charles G. Woychik, Ph.D., Raymond A. Fillion, Tan Zhang, Richard J. Saia, Paul A. McConnelee, and Shane Lewis, GE Global Research; Kishor V. Desai and Patrick Variot, LSI Logic Corporation
MONDAY, AUGUST 18
3:30pm – 5:00pm
ET4
Evolving Technology and Current Issues Panel
Moderator: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
Co-Chair: Lars Boettcher, Fraunhofer IZM
FREE Beer and Pretzels
Monday, August 18
3:30pm – 5:00pm
Come and join the team of industry experts to learn where the technology is heading and the current key issues in packaging, surface mount materials and manufacturing. Experts from industry will first present an overview of current and future technology, current status of lead-free implementation, and experience building new lead-free and packaging. Then, these experts join selected speakers from various ET sessions to answer your questions. Bring your challenging issues/questions from work to get answers from experts who provide unique perspectives based on their experience.
Panelists will include:
Ken Gilleo, Ph.D., ET-Trends LLC (Technology Trends)
Ron Lasky, Ph.D., Indium Corporation, (Lead-Free Materials)
Irene Sterian, Celestica Inc. (EMS Perspective)
Charles Woychik, Ph.D., GE (Embedded Technology)
Joseph Fjelstad, Verdant Electronics
Steve Greathouse, Plexus Corporation
TUESDAY, AUGUST 19
10:00am – 11:30am
SMT1
Solder Paste Printing
Chair: Don Burr, Boston Scientific-CRM
Co-Chair: Todd Woods, Photo Stencil
Tuesday, August 19
10:00am – 11:30am, Fiesta 3
Solder paste printing has historically been the industry’s accepted cause of 40% to 60% of the SMT defects. So even while many may consider this a mature process, the need for miniaturization is continuing to drive technology changes. Very small component apertures now have to sit along side traditional large components. This session will discuss various relevant topics. The first speaker will present a new split squeegee blade concept that helps accommodate simultaneous larger step-up and step-down requirements in the stencil. The second speaker will discuss how to better distinguish between defects that will “self correct” during the reflow process versus defects that will result in true reflowed defects. Finally, the need for smaller apertures has resulted in the need to hold tighter sub-10 micron tolerances. The last speaker will break down the parts of the printing platform to help statically understand what parts of the machine are most critical to achieve the printing accuracy desired.
Squeegee Blade Designs for Step Stencils
William E. Coleman, Ph.D., Photo Stencil
Effect of Solder Paste Printing Defects On End of Line Defects
Rita Mohanty, Ph.D.
Speedline Technologies, Inc.
Understanding the Requirements of the Mass-imaging Platform with Reference to the Impact of Interconnect Miniaturization
Clive Ashmore, DEK Printing Machines
MFX1
Lead-Free Rework and Reballing BGA Packages
Chair: Keith Crane, Riverside Electronics
Co-Chair: Ed Zamborsky, OK International
Tuesday, August 19
10:00am – 11:30am, Coronado D
The transition to lead-free electronic assemblies due to environmental regulation is well known. Due to this changing demand, component manufacturers are moving from lead-bearing to lead-free solders and lead finishes. The resulting shortage of lead-bearing components is resulting in the use of lead-free components in assemblies not necessarily required to be lead-free. This session will cover some of the challenges associated with reworking lead-free solder joints and with reballing BGA (ball grid array) packages. Processes and materials used for lead-free rework and reliability of reballed components will be discussed in detail.
Lead-Free Rework – Challenges for Materials and Processing
Mathias Nowottnick and Andrej Novikov, University of Rostock
Ball Attachment and Reattachment Practices
Bob Wetterman, BEST Inc.
SnPb BGA Reballing Process and Reliability
William Beair and Bill Vuono, Raytheon Company
SOL1
Assessment of Lead-Free Reliability
Chair: Ning-Cheng Lee, Ph.D., Indium Corporation
Co-Chair: Carol Handwerker, Ph.D.
Purdue University
Tuesday, August 19
10:00am – 11:30am, Coronado A
Reliability of lead-free packaging and solder joints is still a territory not well charted. In this session, impacts of reflow ramp rate and mechanical test conditions on packaging and solder joints were investigated. For thermal cycling test, the failure mode was studied by examining the morphology of crack initiation and propagation.
Reliability Impact of Simulated Board Reflow Ramp Rate on Various Surface Mount Packages
Kenneth Thompson and Yanil Cruz, Freescale Semiconductor
Survivability Assessment of SnAg Lead-Free Packaging Under Shock and Vibration Using Optical High-Speed Imaging
Pradeep Lall, Ph.D., Deepti Iyengar, Sandeep Shantaram, Dhananjay Panchagade, and Jeff Suhling, Auburn University – CAVE
Micro Analysis Methods Used for Failure Mechanism Research on Lead-Free Solder Joints
Sang Liu, Ph.D., Tu Yunhua, Li Song, Zhao Xiang, An Tian, and Ye Yuming; Huawei Technologies, Co. Ltd.
DCA1
3D Wafer Level Packaging
Chair: Lars Boettcher, Fraunhofer IZM
Co-Chair: Tom Borkes, The Jefferson Project
Tuesday, August 19
10:00am – 11:30am, Fiesta 1
Through silicon via (TSV) is an enabling technology for three dimensional chip stacking. Besides the mainly used methods deep reactive ion etching (DRIE) and laser drilling for the fabrication of TSV, wet chemical etching can be a considerable option with its highly parallel batch processing possibility. To provide highly reliable TSV, process challenges like metal voiding during filling, uniform via wall material deposition, and active IC surface connectivity need to be controlled. Induced stresses during TSV fabrication may cause cracking of the silicon, lowering the process yield. Easy to use calculation tools help to evaluate potential risks and by that design optimization can be applied. A new 3D-WLCSP technology includes both, thin film processing to enable Flip Chip on wafer bonding as well as the assembly to produce a 3D Face to Face Flip Chip on wafer package. Here the combination of the existing infrastructures for wafer level packaging and high volume Flip Chip assembly allows a new low cost 3D W afer Level Chip Scale Package technology.
A Via-First Approach to Fabricate Through-Silicon Vias Using Anisotropic Wet Etching of (100) Silicon Wafers
Ramachandran Trichur and Xie Shao, Brewer Science, Inc.
Through Silicon Vias (TSV): Design and Reliability
Ephraim Suhir, University of California Santa Cruz, and Sergey Savastiouk, ALLVIA, Inc.
A 3D-WLCSP Package Technology: Processing and Reliability Characterization
Paul Houston and Daniel F. Baldwin, Ph.D., Engent, Inc.; Gene Stout and Ted Tessier, Flip Chip International LLC
TUESDAY, AUGUST 19
1:30pm – 3:00pm
SMT2
Wave Soldering
Chair: Denis Jean, Plexus Corporation
Co-Chair: Peter Biocca, Kester
Tuesday, August 19
1:30pm – 3:00pm, Fiesta 3
Wave soldering today is still the most prominent soldering process for through-hole components. While the wave soldering process has been in the industry for over 40 years, it remains one of the least understood soldering processes. Selective wave soldering has become the preferred method within the last several years with a venue of active SMT component packages on both sides of the board assembly. The lead-free wave soldering is bringing a new set of thermal, chemical and design challenges to the mass soldering process. This session will provide information that will assist the attendee to understand these impacts in their production facilities.
Pb-Free Wave Solder
Ken Hubbard, Cisco Systems, Inc.
Copper Erosion During Wave Soldering, Part III
Chrys Shea, Jim Kenny, and Jean Rasmussen, Cookson Electronics; Girish Wable and Quyen Chu, Jabil Circuit, Inc.; Shiang Teng, San Jose State University, Keith Sweatman, Nihon Superior Co. Ltd.; and Kazuhiro Nogita, Ph.D., University of Queensland
Selective Wave Soldering DoE to Develop DFM Guidelines for Pb and Pb-Free Assemblies
Craig Hamilton, Mario Moreno, Ramon Mendez, German Soto, and Jessica Herrera, Celestica Inc.
MFX2
Cleaning Challenges in Today's Environment
Chair: Laura Turbini, Ph.D., Research in Motion
Co-Chair: Linda Woody, Lockheed Martin
Tuesday, August 19
1:30pm – 3:00pm, Coronado D
High density assemblies, low standoff components such as leadless QFNs, new soldering fluxes and pastes, and the higher temperatures required by lead-free soldering have all made cleaning a major challenge for today’s electronics. The residues under low profile components and from the higher processing temperatures are very difficult to remove and can cause reliability problems. Improved cleaning chemistries and equipment are needed. The speakers in this session will provide important information needed to build a robust cleaning process.
Challenges and Solutions of Cleaning No-Clean Flux Residues from Surface Mount Components
Eric Camden, Foresite
Fluid Flow Mechanics - New Advances in Low Standoff Cleaning
Harold Wack, Ph.D., Joachim Becht, Ph.D., and Umut Tosun, ZESTRON America
Innovative Batch Cleaning Process Design that Removes Lead-Free Flux Residues Under Low Standoff Components
Mike Bixenman, Kyzen Corporation, and Steve Stach, Austin American Technology
MFX3
Assembling with Discretes
Chair: Tom Forsythe, Kyzen Corporation
Co-Chair: Sang Liu, Ph.D.
Huawei Technologies Co., Ltd.
Tuesday, August 19
1:30pm – 3:00pm, Coronado A
This session will look at several aspects of discrete components as they relate to the increase temperature of lead free processing. New finding associated with out gassing of tantalum capacitors, tombstoning of small 0201 chip components, pad design and solder volume will all be discussed in this session. This review of discrete components consists of three papers dealing with this timely topic.
Discrete Test Vehicle
Theeraphong Kanjanupathum, Celestica Inc.
Effect of Component Out-gassing to Solder Defect in SMT Assembly
CW Ooi, Plexus Corporation
TBD
DCA2
Novel Flip-Chip Technology Implementations
Chair: Quan Qi, Ph.D., Cisco Systems, Inc.
Co-Chair: Michael Nadreau, Emerson and Cuming
Tuesday, August 19
1:30pm – 3:00pm, Fiesta 1
In this session, three interesting studies in the area of flip-chip implementations are presented. The first presentation discusses use of non-flow underfill materials in high I/O and fine pitch flip chip applications. The focus of the presentation will be given to the assembly yield characterization and investigation of the impact of underfill void content on reliabilities. The second presentation discusses fine pitch flip chip attachment to flexible carrier. Focus here will be given to the development of a hot bar thermode attach process for large die applications and process control procedures involved. The final presentation discusses a new encapsulation process for system-in-package (SIP) applications. The focus of the talk will be on flip chip stacked die implementations and how the new process name "molded underfill" is applied to help mitigate the stress levels in SIP.
Assembly Yield Characterization and Void Formation Study on High I/O and Fine-Pitch Flip Chip Interconnects Using No-Flow Underfill
Sangil Lee, Ph.D., Daniel F. Baldwin, Ph.D., Myung Jin Yim, and C. P. Wong, Georgia Institute of Technology; Raj Master, Advanced Micro Devices
Fine Pitch Flip Chip Attach to a Flexible Carrier
Charles Woychik, Ph.D., Rayette Fisher, Robert Wodnicki, and Scott Cogan, GE Global Research; Christine Kallmayer, Rafael Jordan, Hermann Oppermann, and Thomas Frisch, Fraunhofer IZM; Barbara Pahl, Technical University of Berlin
New Encapsulation Process for the SiP
Tae Hyun Kim, Sung Yi, Dong-Kuk Kim, Tae Sung Jung, Ki Chan Kim, and Jin Su Kim, Samsung Electro-Mechanics Co., Ltd.
TUESDAY, AUGUST 19
3:30pm – 5:00pm
SMT3
Parameters Affecting OSP Coating
Chair: Nicole Butel, Avago Technologies
Co-Chair: Rob Rowland, RadiSys Corporation
Tuesday, August 19
3:30pm – 5:00pm, Fiesta 1
Lead-free requirements have increased the popularity of Organic Solderability Preservative (OSP) as a surface finish for copper printed circuit board. OSP provides a temporary protection from oxidation but multiple heating cycles in various environments do degrade the surface finish and do affect its solderability. During this session, key parameters for successful solderability of OSP will be presented, secondly the effect of various Oxygen concentrations in Nitrogen reflow atmosphere will be studied in relationship to the surface finish degradation. A relationship between process parameters and surface finish degradation will be provided. Then the reliability of various solder joints will be evaluated, such as lead pull strength, solder joint microstructure, void area percentage and PTH fill.
Optimizing the Organic Solderability Preservative Process (OSP) for Lead-Free Soldering
Michael Carano, OMG Electronic Chemicals
Effect of Oxygen Concentrations in the Reflow Process on the Degradation of Cu OSP Surface Finish Boards
Ursula Marquez de Tino and Denis Barbini, Ph.D., Vitronics Soltec; Wesley Enroth and Aaron Unterborn, Flextronics International
High Temperature OSP Process Recent Advances
Jim Kenny, John Fudala, Zheng Bo, Bob Farrell, ShenLiang Sun, Xingping Wang, Karl Wengenroth, and Dr. Joseph Abys, Enthone Inc., Cookson Electronics
MFX4
Alternate Lead-Free Alloys
Chair: Ron Lasky, Ph.D., PE, Indium Corporation
Co-Chair: Phil Zarrow, ITM Consulting
Tuesday, August 19
3:30pm – 5:00pm, Coronado D
The advent of lead-free soldering with the de-facto SAC305 standard and its close relatives has resulted in poor performance and increased cost in some applications. It is only natural that research for substitute materials would transpire. This session will cover some of the work in this arena, most notably:
Minimization of pad copper dissolution by increasing the copper content of SAC alloys
Improving mechanical shock performance of SAC solder joints by lowering the silver content in the SAC alloy
Processes development and reliability testing of low silver SAC solder spheres
The papers will present process development, reliability data and explanation of the results. This workshop is ideal for the person who wants to be brought up to speed on what is happening in alternative lead-free alloys to improve performance and reduce cost.
Low-Silver BGA Assembly
Chrys Shea and Ranjit Pandher, ALPHA-A Cookson Electronics Company; Girish Wable and Quyen Chu, Jabil Circuit, Inc.; Greg Henshall, Ph.D., Hewlett-Packard; Ahmer Syed, Amkor Technology, Inc.
Implementation of Increased Cu Levels (1%) in SAC Alloys for PBGA Applications
Isabel de Sousa, Donald W. Henderson, Luc Patry, and Robert Martel
IBM Corporation
Research About Application Character of New Lead-free Alloy
Yunji Liu, Huawei Technologies Co., Ltd.
SOL2
Lead-Free Material Behavior and Reliability
Chair: Denis Barbini, Ph.D., Vitronics Soltec
Co-Chair: Randy Schueller, Ph.D., Dell
Tuesday, August 19
3:30pm – 5:00pm, Coronado A
This data driven session, consisting of three original investigations, provides information on the specific gaps that exist in the industry’s understanding of lead-free materials, behavior, performance, and ultimately lifetime modeling. The root cause of specific defects such as brittle fractures observed after drop and shock testing, open circuits observed during ATC testing, and the quantification of creep behavior under load are studied and detailed in this session.
Analysis of Failure Mechanisms of Lead-Free Alloys Under Continuous Monitoring
Maurice N. Collins, Mauro V. Aguanno, Michael Reid, Claire Ryan, and Jeff Punch, Stokes Institute-University of Limerick
Microvoid Formation at Copper-Solder Interfaces During Annealing: A Systematic Study of the Cause
Santosh Kumar, Carol Handwerker, Ph.D., and Xu Nie, Purdue University; Joseph Smetana, Alcatel-Lucent; David Love, Sun Microsystems, Inc.; James Watkowski, MacDermid Inc.; and Richard Parker, Delphi Electronics & Safety
In-Situ Creep Observation of Joint-Scale SAC Solder Samples Under Shear Load
Dominik Herkommer, Michael Reid, and Jeff Punch, Stokes Institute-University of Limerick
WEDNESDAY, AUGUST 20
8:00am – 9:30am
SMT4
Backward Compatibility
Chair: Tim Ginzburg, Celestica Inc.
Co-Chair: Mumtaz Bora, Kyocera Wireless
Wednesday, August 20
8:00am – 9:30am, Monterrey 1
The conversion to Pb-free solder has already been implemented in consumer products. However, for certain high performance, mission critical applications, Sn-Pb solders are still pervasively used. Some studies will be highlighted in this session to identifying specific assembly parameters and thermo mechanical reliability, published on the correlation between assembly condition (peak temperature and time-above-liquids), thermo mechanical, aging and mechanical reliability. Our discussion focuses on best practices for materials, processes and controls for mixed alloy environments.
Rework Practices in a Mixed Alloy Environment
Bob Wetterman, BEST Inc.
Impact of Backwards Compatible Assembly on BGA Thermomechanical Reliability and Mechanical Shock, Pre- and Post-Aging
Mudasir Ahmad, Kuo-Chuan Liu, and Jie Xie, Cisco Systems, Inc.
Evaluating the "Reverse Compatibility" of Solder Joints – Part 2
William Russell, Raytheon Professional Services LLC; Dennis Fritz, SAIC, Inc.; and Gary S. Latta, Crane Division, Naval Surface Warfare Center
MFX5
The 01005 Component Assembly Process
Chair: Joseph Belmonte, BOSE Corporation
Co-Chair: Tom Borkes, The Jefferson Project
Wednesday, August 20
8:00am – 9:30am, Fiesta 3
With the advent of 01005 (10 x 5 mil or 0.25 x 0.125 mm) passives and lead-free assembly at the same time, there is a strong need to develop an optimized process for the assembly of these miniscule passives. We hear so much about “01005s” that we can become jaded as to how small they really are. Their width (5 mils is only slightly larger than the thickness of a human hair and their length about the thickness of a sheet of resume paper! So it should come as no surprise that assembling 01005s with lead-free solder paste is a great challenge. This session will present both experimental and process qualification data that examines all aspects of the 01005 component assembly process, such as the solder paste printing process.
Production Process Qualification for 01005 Size Passive Components
Fredrik Mattson and Dongkai Shangguan, Ph.D., Flextronics International
The Effect of Stencil Design and Enclosed Pump-Head Printing Process on 01005 Paste Transfer
Arun S. Ramasubramanian and Daryl Santos, Ph.D., Binghamton University; Rita Mohanty, Ph.D., Speedline Technologies, Inc.
Assembly Process Challenges for 01005 Components
Rita Mohanty, Ph.D., Speedline Technologies, Inc.; Tony Longo and Brian Smith, Kester
AAT1
Package Advancements
Chair: Hugh Roberts, Atotech USA, Inc.
Co-Chair: Scott Buttars, Intel Corporation
Wednesday, August 20
8:00am – 9:30am Coronado A
This session will provide insight into some of the latest advances in surface mount packaging. The first presentation will introduce a new type of plastic package that combines an exposed pad QFP with a Quad Flat No Lead (QFN) package. Next, data on the board assembly and reliability of another new BGA package type, the Redistributed Chip Package (RCP), will be presented. With this package type, which does not contain wirebond or flip chip connections, the dielectric and package routing layers are built up on the die to form the package. Lastly, a copper surface treatment technique will be advanced that increases the adhesion of the mold compound and therefore leads to reduced interfacial delamination at Pb-free reflow temperatures.
Board Design, Surface Mount Assembly and Board Level Reliability Aspects of FusionQuad™ Packages
Ahmer Syed, WonJoon Kang, Gary Hamming, and YeonHo Choi, Amkor Technology Inc.; Sundar Sethuraman, Flextronics International
Board Design, Surface Mount Assembly and Board Level Reliability Aspects of FusionQuad™ Packages
Andrew Mawer, Freescale Semiconductor
Enhancing Package Reliability Through Delamination Reduction
Bruce Lee, John Ganjei, and Dan Hart, MacDermid Inc.
SUB1
Surface Finish Reactions
Chair: Don Cullen, MacDermid Inc.
Co-Chair: Dave Hillman, Rockwell Collins
Wednesday, August 20
8:00am – 9:30am, Coronado D
Circuit board surface finishes continue to evolve as the industry finds more ways to use them, as the suppliers find new ways to improve functionality, and as new technical issues are discovered. In this session, we will explore some new methods to overcome existing surface finish limitations. Our first speaker will discuss the ability to achieve a NiPdAu finish with gold wirebonding functionality, while maintaining the solder joint reliability required of post-RoHS manufacturing. Next, we will discuss the continuing effort to prevent Black-Pad Nickel, with some new insights into nickel oxidation during immersion gold deposition. Lastly, we will investigate ways to predict intermetallic growth at the copper-tin interface of immersion tin with new methods for characterizing and studying this very important junction.
Investigation of IMC Growth in Tin Surface Finish and its Effect on Solderability in FC-CSP Packaging
HyunJung Lee, Samsung Electro-Mechanics, Co., Ltd.
Nickel Deposit in ENIG Plating
Donald Gudeczauskas and George Milad, Uyemura International
Electroless Ni-P/Pd/Au Plating for High Density Semiconductor Package Substrates
Yoshinori Ejiri, Takehisa Sakurai, Shuuichi Hatakeyama, Shigeharu Arike, Hitachi Chemical Co., Ltd.; and Kiyoshi Hasegawa, Hitachi Chemical Electronics Co. Ltd.
PRC1
The Automated X-Ray Inspection (AXI) Technology Process in the Manufacturing Environment
Chair: Robert Jukna, Jabil Circuit, Inc.
Co-Chair: Steve Butkovich, Cisco Systems, Inc.
Wednesday, August 20
8:00am – 9:30am, Fiesta 1
For over ten years, we have been using X-ray technology in the manufacturing environment to produce a better quality output from Manufacturing. In today’s session you will hear from the industry leaders on how to make the X-Ray inspection process better through PCB design, process design, as well as X-Ray system level tools. Without a stable inspection process, there is a fine balance of thresholds between defect detection, defect escapes and false failures. As the AXI process varies, the current thresholds will no longer apply, resulting in expensive rework of good product or defect escapes to your customers. Join us in the session to benefit from the experience of the leaders of AXI and Manufacturing Technology.
A Suggested Process for Detecting Counterfeit Components
David Bernard, Ph.D., Dage Precision Industries Inc., and Bob Willis, ASKbobwillis.com
An Innovative Use of AXI to Meet Zero-Defect Quality Standards – CAD-Driven Automatic X-ray Soldered Joint Inspection
Kathleen Brockdorf, Tobias Neubrand, and Thomas Mayer, phoenix/x-ray Systems + Services
Computed Tomography – A 3D View Into Electronics Assemblies
Frank Cosentino and Robert Meller, VJ Electronix, Inc.
WEDNESDAY, AUGUST 20
10:00am – 11:30am
SMT5
SMT Connector Technology
Chair: Jim Zanolli, Teka Interconnection Systems
Co-Chair: Rich Freiberger, ZF Array Technology
Wednesday, August 20
10:00am – 11:30am, Monterrey 1
Increasing system speed requirements are driving demand for SMT area array connectors and other high density connection schemes. These requirements and RoHS compliance present unique challenges for assembly cost efficiency and reliability. This session will discuss SMT connector issues relating to area array connector reliability, BGA connector to PCB assembly methodologies, and new flexible printed circuit attachment technologies.
Process Development and Reliability Study with Anisotropic Conductive Film Bonding as a Replacement for Surface Mount Connectors and Hotbar Soldering
Jonas Sjoberg, Alvin Goh, Manickavasagar Minor, and Dongkai Shangguan, Ph.D., Flextronics International
Area Array Connectors: Transition to Lead-free
Heather McCormick, Celestica Inc.; Don Harper, FCI; Alex Chan and
Richard Coyle, Ph.D., Alcatel-Lucent
Case Study - BGA Connector Assembly Process Characterization
Alfred Ho, Cisco Systems, Inc.
MFX6
Package on Package (PoP)
Chair: Gene Dunn
Panasonic Factory Solutions of America
Co-Chair: Kirk Van Dreel, Plexus Corporation
Wednesday, August 20
10:00am – 11:30am, Fiesta 3
Package on Package assembly or PoP continues to gain broad acceptance in handheld products by integrating logic devices in the bottom package and memory in the top package. Increased product functionality and lower profile package requirements place ever increasing demands on the PoP package design and assembly material requirements. This session will examine a new high density PoP design that satisfies the high I/O requirements while minimizing package warp during reflow. In addition, papers that compare different flux types used in PoP assembly and the use of 2D & 3D X-Ray inspection for stacked packages will be presented.
Surface Mount Assembly for High Density PoP (Package-on-Package) Utilizing TMV™ (ThruMoldVia™) Technology
Joanna Wildhart, Panasonic Factory Solutions of America, and Curtis Zwenger, Amkor Technology, Inc.
Flux Materials for Increased Yield of Package on Package Devices
Brian Toleno, Ph.D., Mark Currie, Tim Lawrence, and Gavin Jackson, Henkel Corporation
Investigating Defects in 3D Packages Using 2D and 3D X-ray Inspection
Evstatin Krastev, Dage Precision Industries, Inc.
AAT2
Thermal/Mechanical Reliability of BGAs
Chair: Ahmer Syed, Amkor Technology, Inc.
Co-Chair: Dong Hyun Kim, Ph.D.
Cisco Systems, Inc.
Wednesday, August 20
10:00am – 11:30am, Coronado A
The board level reliability of BGAs remains one of the critical factors in package design and selection. Finer pitch BGAs, application specific load conditions, and the migration to Pb free solder are the three top challenges faced by packaging industry for board level reliability assessment and enhancement. The papers selected for this session not only show the implication of these factors on board level reliability, but also present the methodology for reliability evaluation.
Process and Reliability Research of 0.4mm Pitch CSP
Jakey Tsin, Michael Meilunas, Zhiwei Song, Bingtao Xi, Shoukai Zhang, and Fujiang Sun, Huawei Technologies Co., Ltd.
Vibration Failure Assessment Methodology for the Fatigue Life of Ball Grid Array (BGA) Solder Joints
Mei-Ling Wu, National Cheng Kung University, and Donald Barker, University of Maryland
Effects of Thermal and Mechanical Fatigue on Organic SAC 305 FPBGA Packages
Arv Sinha, IBM Corporation
SUB2
Reliability of Pb-Free Solder Interconnects
Chair: Carol Handwerker, Ph.D.
Purdue University
Co-Chair: Dennis Fritz, MacDermid Inc.
Wednesday, August 20
10:00am – 11:30am, Coronado D
With the possibility of Pb-free solder interconnects being used in high reliability systems now exempt from RoHS, there is a need for thorough, detailed reliability data for new components, materials, and systems. Furthermore, the data must be obtained using standard performance tests specifically developed for evaluating Pb-free solders for high performance applications and harsh environments. In this session, The first presentation will describe the new Government Electronics Industries Association (GEIA) performance testing protocol for lead-free electronic interconnects in AHP (Aerospace and High Performance) products. The two talks that follow will report results of two studies on the effects of surface finish on solder joint manufacturability as on well reliability.
GEIA-STD-0005-3: Performance Testing for Aerospace and High Performance Electronic Interconnects Containing Pb-free Solder and Finishes
Anthony Rafanelli, Ph.D., Raytheon Company
PWB Surface Finish Reliability
Bill Vuono, Raytheon Company
Reliability of Tin-Silver-Copper Lead-Free Solder Interconnects Under Thermal-Mechanical Loading With Different PWB Surface Finishes
Nikhil Lakhakar, Mohammad Hossain, Puligandla Viswanadham, and Dereje Agonafer, University of Texas at Arlington
PRC2
SMT Process Optimization and Test and Inspection Methods for Identifying Solder Defect Joints That Are Cost Effective
Chair: Salvatore Rampaul-Pino, Vision Research
Co-Chair: Dale Lee, Plexus Corporation
Wednesday, August 20
10:00am – 11:30am, Fiesta 1
This session will discuss how using the approach of zero tolerance for defects will allow one to determine if the process is optimized. Additionally, it will allow one to determine the step(s) to achieve best in class surface mount technology (SMT) quality. Also, this session will discuss the non-destructive methods and techniques for identifying ball grid array (BGA) solder joint opens and cracks. Finally, this session will discuss the techniques that allow 100% in-line inspection to be cost effective and that do not reduce cycle time.
Using "Zero Defects" Philosophy to Incorporate Process Optimization to Achieve Best in Class SMT Quality
Robert Gray, Siemens Energy & Automation, Inc.
Innovations in Solder Paste Inspection Technology
Zhen (Jane) Feng, Ph.D., Juan Carlos Gonzalez, Sea Tang, and Murad Kurwa, Flextronics International; Evstatin Krastev, Ph.D., Dage Precision Industries, Inc.
Solder Paste Inspection Using 2D and 3D Technique
Rita Mohanty, Ph.D., and Vatsal Shah, Speedline Technologies, Inc.; Paul Haugen and Laura Holte, CyberOptics Corporation
WEDNESDAY, AUGUST 20
1:30pm – 3:00pm
SMT6
The Return of Vapor Phase
Chair: Girish Wable, Jabil Circuit, Inc.
Co-Chair: Jeff Kennedy, Celestica Inc.
Wednesday, August 20
1:30pm – 3:00pm, Monterrey 1
Vapor phase is back and it’s cooler than ever. When the topic was introduced last year at SMTAI it was received with great enthusiasm. The session returns with the latest in technology development, equipment modifications and demonstrates how assemblers are using this technology to keep manufacturing lean and effective.
Today's Vapor Phase Soldering: An Optimized Reflow Technology for Lead-Free Soldering
Helmut Leicht, IBL-Löttechnik GmbH
Vapor Phase Technology and Its Benefits
Allen W. Duck, A-Tek llc
The Advantages of Vapor Phase Processing in RoHS-Compliant Assembly
Chris Munroe, EPIC Technologies
MFX7
Advanced Environmental Product Compliance Issues
Chair: Bill Barthel, Plexus Corporation
Co-Chair: Scott Anson, Ph.D.
Rochester Institute of Technology
Wednesday, August 20
1:30pm – 3:00pm, Fiesta 3
This session covers work done to better understand a variety issues that have been escalated as the industry continues to work toward environmental compliance. Lower silver levels in SAC alloys along with trace elements have been gaining interest for enhanced performance. This session will explore the reliability of these alloys under a number of different conditions when used with various PCB surface finishes. Attendees of this session will get an up-to-date assessment of immersion silver finishes in corrosive environments. Finally, new interest in removing halogens from solder fluxes is investigated. Anyone interested in gaining insight on leading product compliance issues will be sure to find value in this session.
Reliability Testing of Doped Lead-free Solder Alloys with Varying Silver Content
Mauro Aguanno, Maurice Collins, Michael Reid, Claire Ryan, and Jeff Punch,
Stokes Institute-University of Limerick
Creeping Corrosion of PWB Surfaces in Harsh Sulfur Containing Environments
Ernest Long, Ph.D., and Lenora Toscano, MacDermid, Inc.
Halogen Free Solder Pastes and Fluxes: Implementation Challenges
Tim Jensen and Amanda Whittamore, Indium Corporation
AAT3
Mechanical Stress Characterization and Performance Improvements
Chair: Marie Cole, IBM Corporation
Co-Chair: Reza Ghaffarian, Ph.D.
Jet Propulsion Laboratory
Wednesday, August 20
1:30pm – 3:00pm, Coronado A
Mechanical stresses from assembly processing and field applications continue to be of concern. Learn new techniques for assessing the mechanical behavior of assemblies and methods to optimize robustness. Prevent component and solder joint damage by optimizing the PCB panel design through understanding of the stresses applied during the board singulation process, and select the appropriate de-panelization process for your assembly. Select the optimum corner glue material to enable fine pitch BGA packages to withstand mechanical loading. Gain insight about how the package and board characteristics of FCPBGA assemblies impact the flexural resistance of the board assembly solder-joints. These presentations provide guidance to improve mechanical reliability performance through design, material and process optimization.
Using Strain Gauge Analysis to Optimize the PCB Design and Minimize the Risk of Component Damage During Assembly De-Panelization
Mark Logterman, Mudasir Ahmad, Anthony Burton, and Lavanya Gopalakrishnan, Cisco Systems, Inc.
Methodical Approach in Selecting Reworkable Corner Glue for BGA Packages Mechanical Stress Protection
Ching Ching Chong, Cheng Siew Tay, Renn Chan Ooi, and Lian Huat Ng, Intel Products (M) Sdn. Bhd.
Mechanical Behavior of Large Lidded Flip Chip BGA Organic Packages Under Flexural Loading
Hua Lu, Ph.D., Ryerson University
SUB3
Impact of RoHS on Substrates, Alloys and Finishes
Chair: Srinivas Chada, Ph.D., Medtronic Inc.
Co-Chair: Laura Turbini, Ph.D.
Research in Motion
Wednesday, August 20
1:30pm – 3:30pm, Fiesta 3
Restriction of Hazardous Substances Directive (RoHS), adopted in February 2003 by the European Union, took effect on July 1, 2006. This directive restricts the use of six hazardous materials, namely, lead , mercury, cadmium hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ether (PBDE) in the manufacture of various types of electronic and electrical equipment. The effect of RoHS is widespread across a variety of materials used in electronics manufacturing. Examples include removal of Pb from solder alloys and surface finishes, eliminating bromine as a flame retardant in PCBs, etc. In turn, the elimination of the ‘dreaded six’ spurred new alloy and process developments in a very short span, but also exposed the industry to problems with little understanding, such as tin pest, Sn whiskers, higher reflow temperatures, and an assortment of reliability concerns. This session tries to answer some of these worries. In the first paper we explore the results from an ongoing research on tin pest. The next paper investigates an anti-corrosion treatment that can mitigate Sn whiskering. Finally, the last paper in this session provides a summary of the findings from iNEMI halogen-free PCB material project by comparing laminate materials, their processability, and reliability.
An Ongoing Investigation into the Tin Pest Phenomena: 2.5 Years and Counting
Dave Hillman, Rockwell Collins
Anti-corrosion Solution for Reduction and Prevention of Corrosion Whiskers
Kevin Martin, Atotech USA; Jürgen Barthelmes, Ph.D., and Olaf Kurtz, Ph.D., Atotech Deutschland GmbH
iNEMI Halogen-Free PCB Material Evaluation Study
Stephen Tisdale and Gary Long, Intel Corporation; Roger Krabbenhoft, IBM Corporation; Terry Fischer, Hitachi; and Kostas Papathomas, EI
Non-Destructive Techniques for Identifying Defect in BGA Joints: TDR, 2DX, and Cross-section/SEM Comparison
Mike Powers, Agilent Technologies
EMS1
Teaming for Efficient Manufacturing
Organized by Mike Buetow
UP Media Group/Circuits Assembly Magazine
Sue Mucha, Powell-Mucha Consulting, Inc.
FREE with VIP or Technical Conference Registration!
Chair: Sue Mucha, Powell-Mucha Consulting, Inc.
Co-Chair: Chelsey Drysdale, Circuits Assembly Magazine
Wednesday, August 20
1:30pm – 3:00pm, Fiesta 1
The electronics manufacturing services (EMS) has grown beyond simply providing a high quality, alternate manufacturing venue. Today’s EMS providers are expected to be problem solvers capable of addressing the entire product realization process. This session highlights some best practices and identifies needed areas of improvement. While topic specific Q and A will follow each speaker, time at the end will be allotted for a panel discussion where all speakers will address questions related to process efficiency and emerging trends.
Emerging Technologies in RF Design and Implications on Design for Manufacturability and Testability in Outsourced Production
Roger Allcorn, Syncro Corporation
Teaming for Increased Process Visibility
Jeff Roberts, Clover Electronics
EMS Audits: What We've Learned
Phil Zarrow, ITM Consulting
WEDNESDAY, AUGUST 20
3:30pm – 5:00pm
AAT4
Impact and Fatigue Reliability of Lead-Free Solders
Chair: Dan Baldwin, Ph.D., Engent, Inc.
Co-Chair: Jennie Hwang, Ph.D., H-Technologies Group
Wednesday, August 20
3:30pm – 5:00pm, Coronado A
The transition to lead-free solder alloys has prompted concerns with mechanical fatigue and impact reliability of lead-free interconnects. Techniques for reliability testing of mechanical fatigue and impact resistance continue to evolve to provide better predictability of field failures and more rapid test cycle times in cost sensitive applications. In this session, the impact and fatigue reliability of various lead-free interconnect systems will be examined. Highlights include investigations into new test techniques, high temperature performance, and correlation of reliability test performance and field failures.
The Superior Drop Test Performance of SACT Solders and Its Mechanism
Ning-Cheng Lee, Ph.D., Indium Corporation
Investigation of Solder Joint Reliability Through Impact Fatigue Loading
Brian Roggeman, Pradosh Guruprasad, and James Pitarresi, Unovis-Solutions
TBD
SUB4
Unbiased Debate Separating Hearsay from Truth Regarding Surface Finish Defects
Moderator: Srinivas Chada, Ph.D., Medtronic Inc.
Co-Chair: Girish Wable, Jabil Circuit, Inc.
Wednesday, August 20
3:45pm – 5:15pm, Coronado D
FREE beer and pretzels!
In the previous years we used this panel effectively to educate and understand the issues associated with various surface finishes. Buzz words such as 'black pad,' 'tin whiskers,' and 'champagne voiding' are rife in the electronics industry, but how much does one know about them even after several years of using ENIG, plated Sn, immersion Ag…etc.? With the advent of WEEE, RoHS, and Pb-free the search for a compatible surface finish continues. In this panel discussion we continue discussing ENIG, ENEPIG, high temperature OSPs, immersion Sn and immersion Ag as surface finishes for the present and future, as well as the defects associated with their use from OEM, CEM, and vendor perspectives.
Panelists include:
Don Cullen, MacDermid Inc.
Carol Handwerker, Ph.D., Purdue University
Dave Hillman, Rockwell Collins
Gerard O’Brien, Solderability Testing and Solutions
Polina Snugovsky, Ph.D., Celestica Inc.
EMS2
Managing Our Suppliers and Ourselves
Chair: Mike Buetow, Circuits Assembly Magazine
Co-Chair: Rod Howell, Libra Industries
Wednesday, August 20
3:30pm – 5:00pm, Fiesta 1
FREE with VIP or Technical Conference Registration!
From the OEM perspective, outsourcing is a means to shed headaches and cost. But contracting work isn’t the same as eliminating problems: it simply moves them down the supply chain, and in some cases, even magnifies them. EMS companies faced with managing complex supply chains must learn how to turn the microscope on all their internal processes – be they sales, procurement, processing or quality assurance. And they must learn how to identify not only the proper combinations of data collection and analyses, but also the right personnel.
Turning Your Smallest Customer into Your Biggest
Craig Arcuri, NBS Design
Avoiding and Resolving Disputes over Unsatisfactory Components
Kristal Snider, ERAI
Ensuring Supply Chain Materials Integrity
Jed Jones, Inovar
BUS1
Competitive Strategies for Manufacturing in a Global Economy
Chair: Pradeep Lall, Ph.D., Auburn University
Co-Chair: Gary Tanel, Allegiance Capital Corporation
Wednesday, August 20
3:30pm – 5:00pm, Monterrey 1
The session focuses on various aspects related to manufacturing in the global economy. Different issues relevant to manufacturing have been discussed in three papers. The first paper targets the cost structure of lower-cost regions and the future strategy of US companies in dealing with the global competitive pressures. The second paper deals with the project management related manufacturing strategies for dealing with the shortened product development cycle times. The third paper discusses the process capability index, a metric which is often used in the context of six-sigma quality.
…Like Holding "the Wolf by the Ears…" The Key to Regaining Electronic Production Market Share: Breaking Free of the Division of Labor Manufacturing Model in High Labor Cost Global Regions
Tom Borkes
Applying Project Management Methodologies in Electronics Manufacturing
Leopold A. Whiteman, Jr., PM Solutions
Process Capability Index: A Better Way to Assess Equipment Capability
Rita Mohanty, Ph.D., Speedline Technologies, Inc., and Daryl Santos, Ph.D., Binghamton University
THURSDAY, AUGUST 22
8:00am – 9:30am
LF1
Lead-Free Alloy Alternatives
Chair: Gregory Henshall, Ph.D. Hewlett-Packard
Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
Thursday, August 21
8:00am – 9:30am, Coronado A
Within the past 1-2 years, the industry has seen a proliferation in the number of Pb-free solder alloy choices. The increasing number of Pb-free alloys provides both opportunities and challenges to the industry. This session will begin with a presentation of the results from an iNEMI study into the present state of industry knowledge on "alternative" Sn-Ag-Cu alloys and an assessment of critical gaps. This will be followed by a panel discussion with experts from all segments of the industry, including solder suppliers, EMS providers, component manufacturers, and OEMs.
iNEMI Speakers Include:
Gregory Henshall, Ph.D., Hewlett-Packard
Polina Snugovsky, Ph.D., Celestica Inc.
Richard Coyle, Ph.D., Alcatel-Lucent
Panelists Include:
Gregory Henshall, Ph.D., Hewlett-Packard
Polina Snugovsky, Ph.D., Celestica Inc.
Richard Coyle, Ph.D., Alcatel-Lucent
Bill Barthel, Plexus Corporation
Keith Sweatman, Nihon Superior Co. Ltd.
Ning-Cheng Lee, Ph.D., Indium Corporation
Robert Kinyanjui, Ph.D., Sanmina-SCI Corporation
THURSDAY, AUGUST 22
10:00am – 11:30am
LF2
High Complexity, High Reliability Lead-Free Case Studies, Part 1
Chair: Matt Kelly, IBM Corporation
Co-Chair: Richard Coyle, Ph.D., Alcatel-Lucent
Thursday, August 21
10:00am – 11:30am, Coronado A
Although the majority of products within electronic consumer market segments have now switched to lead-free printed circuit board hardware assembly, it is clear that many technology / supply chain challenges still remain to ensure high quality, reliability, and yield levels for high reliability application environments. As many of the industry's OEM and CM firms prepare position statements for the upcoming RoHS exemptions review, it is important to understand both the successes and challenges associated with high complexity / high reliability electronics manufacturing. This session is intended to showcase these issues through case study involving real product qualification and testing.
Improving Hole-Fill in Lead-Free Wave Soldering of Thick Printed Circuit Boards with OSP Finish
J. Li, P-F Tsai, and K. Srihari, Binghamton University; C.C. Chew, M. Abtew, and R. Kinyanjui, Ph.D., Sanmina-SCI-Corporation
The Path of Taking High Reliability Products to Lead-Free
Alex Chan, Alcatel-Lucent Canada Inc.
Lead-Free Feasibility Program: Assembly and Testing of a Functional Military Avionics Unit
Dave Hillman and Matt Hamand, Rockwell Collins
THURSDAY, AUGUST 22
1:00pm – 2:30pm
LF3
High Complexity, High Reliability Lead-Free Case Studies, Part II
Chair: Matt Hamand, Rockwell Collins
Co-Chair: Brian Toleno, Ph.D.,
Henkel Technologies
Thursday, August 21st
1:00pm – 2:30pm, Coronado A
Although the majority of products within electronic consumer market segments have now switched to lead-free printed circuit board hardware assembly, it is clear that many technology/supply chain challenges still remain to ensure high quality, reliability, and yield levels for high reliability application environments. As many of the industry's OEM and CM firms prepare position statements for the upcoming RoHS exemptions review, it is important to understand both the successes and challenges associated with high complexity/high reliability electronics manufacturing. This session is intended to showcase these issues through case study involving real product qualification and testing.
Test Data Requirements for Assessment of Alternative Pb-Free Solder Alloys
Helen Holder, Gregory Henshall, Ph.D., Aileen Maloney, Elizabeth Benedetto, Kris Troxel, Guillermo Oviedo, Jian Miremadi, and Michael Roesch, Hewlett-Packard
A Case Study for Transitioning Server Motherboards to Lead-Free
W. Ables, J. Fitch, and R. Schueller, Ph.D., Dell Inc.
Lead-Free Card Assembly Advances and Challenges for Server PCBA's
Matthew Kelly, Marie Cole, and Jim Wilcox, IBM Corporation; Simin Bagheri, Craig Hamilton, Heather McCormick, and Irene Sterian, Celestica Inc.
THURSDAY, AUGUST 22
3:00pm – 5:00pm
LF4
Lead-Free Reliability
Chair: Jean-Paul Clech, EPSI, Inc.
Co-Chair: Kola Akinade, Ph.D., Scientific Atlanta, A Cisco Company
Thursday, August 21
3:00pm – 5:00pm, Coronado A
Given the proliferation of lead-free alloy compositions, much work remains to be done to achieve the same qualitative and quantitative understanding of lead-free attachment reliability as for standard SnPb assemblies. Papers in this session provide much needed contributions to the industry's knowledge-base on lead-free solder joint reliability and related issues. Test results are presented for several alloys (SAC & SnCu-based) and mixed assemblies under mechanical (shock and vibration) and/or thermal cycling conditions. The first paper investigates the effect of thermal aging on the performance of SAC305 assemblies under mechanical shock conditions. The next two papers provide detailed test results and a template for the minimum amount of testing needed to characterize the attachment reliability of a particular lead-free alloy (SnCu-based) under a wide range of conditions (thermal, shock & vibration) and for a variety of component types. The last paper provides insight in the effect of dwell time on solder joint reliability under accelerated thermal cycling conditions for SAC305, SnPb and mixed assemblies.
Study on Dynamic Shock Performance of Lead-Free SAC305 Solder Joint Under Different Aging Conditions
Dong Hyun Kim, Ph.D., Cisco Systems, Inc.
Reliability Testing of Ni-Modified SnCu and SAC305-Accelerated Thermal Cycling
Joelle Arnold, DfR Solutions, and Keith Sweatman, Nihon Superior Co., Ltd.
Reliability Testing of Ni-Modified SnCu and SAC305-Shock and Vibration
Joelle Arnold, DfR Solutions, and Keith Sweatman, Nihon Superior Co., Ltd.
A Comprehensive Solder Joint Reliability Study of SnPb and Pb Free Plastic Ball Grid Arrays (PBGA) Using Backward and Forward Compatible Assembly Processes
Richard Coyle, Ph.D., Alcatel-Lucent; Steven Kummerl, Texas Instruments; Peter Read, Debra Fleming, Richard Popowich, John Manock, and Aaron Unterborn, Flextronics International
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