| Time |
|
Activity |
|
Speaker |
08:30
8:30am |
|
Registration |
|
|
09:00-11:00
9:00am-11:00am |
|
Exhibitor Set Up |
|
|
10:00-11:00
10:00am-11:00am |
|
Session
TA1:
Package on Package |
|
|
Process and Assembly Methods for
Increased Yield of Package on Package Devices |
|
Brian Toleno, Ph.D. and Dan Maslyk,
Henkel Corporation
|
|
|
Surface Mount Assembly Challenges for
High Density PoP (Package-on-Package) Utilizing SoP(
Solder-on-Pad) Technology |
|
Joanna Wildhart,
Panasonic Factory Solutions Company of America; Moody Dreiza, Amkor Technology Inc.
|
|
|
Session
TA2:
Area Array |
|
|
µPILR™Package Platform-A Higher Density
Package-on-Package Innovation for Next Generation Electronics
|
|
Vern Solberg, Tessera Inc. |
|
|
BGA Coplanarity
Reduction During the Ball Attach Process
|
|
Rick Lathrop, Hereaus Contact Materials Division |
11:00- 13:00
11:00am-1:00pm |
|
Lunch Break With Exhibitors
|
|
|
13:00- 14:30
1:00pm-2:30pm |
|
Session
TP1:
Stacked Die and TSV |
|
|
Market Drivers and Cost Analysis for 3D TSV |
|
Eric Mounier, Ph. D., Jérome Baron, and Jean-Christophe Eloye, Yole Development
|
|
|
Cost Effective Copper TSV Interconnect Integration
|
|
Paul Siblerud, Semitool, Inc. |
|
|
Improvements to Through Silicon Vias or TSVs |
|
Phil Marcoux, TPL Group
|
|
|
Session TP2:
Solderability |
|
|
Effects of Storage Environments on the
Solderability of Nickel-Palladium-Gold Finish With Pb-Based and Pb-Free
Solders
|
|
Edwin Lopez, Paul Vianco, Samuel
Lucero, and Carly George, Sandia National Laboratories |
|
|
Effect of Process Variations on Solder
Joint Reliability for Nickel-Based Surface Finishes |
|
Hugh Roberts, Atotech USA Inc.; Sven
Lamprecht, Gustav Ramos, and Christian Sebald, Atotech Deutschland GmbH.
|
|
|
Impact of Soldering Atmosphere on Solder
Joint Formation |
|
Ursual Marquez de Tino and Denis
Barbini, Ph.D., Vitronics-Soltec; Wesley Enroth, Flextronics
|
|
|
|
|
|
14:30- 15:00
2:30pm-3:00pm |
|
Coffee Break With Exhibitors |
|
|
|
|
|
|
|
15:00- 17:00
3:00pm-5:00pm |
|
Session
TP1:
Stacked Die and TSV (Continued) |
|
|
Technologies for 3D Heterogeneous
Integration |
|
M.J. Wolf, P. Ramm, and H. Reichl, Fraunhofer IZM
|
|
|
Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding |
|
Shari Farrens, Ph. D., SUSS MicroTec
|
|
|
Advanced DRAM Si and Packaging
Technology Status and Future Directions
|
|
Jung H. Yoon, Ph.D., IBM Integrated Supply
Chain |
|
|
Update on the Evaluation of Stacked Die
Packages Using Acoustic Micro Imaging
|
|
Janet Semmens, Sonoscan, Inc. |
|
|
Session
TP3:
High Density Substrate Advances |
|
|
HDI Via Architecture Effect on
SiP Design Flexibility and Constraints
|
|
Happy Holden, Mentor Graphics |
|
|
Sub-10µm Line/Spaces on Organic
Substrates for Next Generation System on Package (SOP) and
Flip-Chip Packaging |
|
Venky Sundaram, Fuhan Liu, Hunter Chan,
Mahadevan Iyer, and Rao Tummala, Georgia Institute of Technology;
Hugh Roberts, Atotech USA
|
|
|
Packaging Substrate Technologies Trend
in Japan |
|
Henry Utsunomiya, Interconnection
Technologies, Inc.
|
|
|
Defect Structure and Failure Mechanism of PTH Electrodeposits
|
|
Tu Yunhua, Liu Sang, Sun Xiaoyan, and Ju Yuandao, Huawei Technologies Co., Ltd. |
17:15- 18:00
5:15pm-6:00pm |
|
Keynote
Presentation 1 |
| |
|
The Science & Engineering Workforce and
National Security |
|
Robert Kavetsky, Energetics Technology Center; David K. Anand, Ph.D.,
University of Maryland; and Michael Marshall, Department of Navy(retired) |
18:00- 19:00
6:00pm-7:00pm |
|
Welcome Reception With Exhibitors |
|
|
