Pan Pacific Microelectronics Symposium
Microelectronics Symposium
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THANK YOU
to our 2017 Supporters!



"The Pan Pac Conference offers an opportunity for leaders across the globe to meet and share technical knowledge, collaborate with strategic focus in a friendly environment, and to leverage the opportunity to forge lasting business relationships. This is the longest running event within the SMTA Association and it is a unique conference that ties technology and business together 
in one forum. "

 -Jeff Kennedy
Celestica Inc. 
Questions?


October 2016 Newsletter
Volume 2.3 
February 6-9, 2017
Sheraton Kauai Resort
Kauai, Hawaii



The SMTA Pan Pacific Conference continues its world class tradition in 2017 with keynote speakers such as Michael Pecht of CALCE, Jack Peregrim of Paragon Development and Thomas Brunschwiler of IBM Research-Zurich!  Leaders from around the world, attracted by the level and quality of presenters, also value the high level interactions with business and technology leaders attending from throughout Europe, Asia, the Americas and Australia. Learn about the latest advances in 2.5D and 3D Electronics, wearable electronics, the internet of things, high reliability applications.
 
One key distinction of the Pan Pacific remains the glimpses of both future technologies and strategic directions. For example, Tsuyoshi Kawanishi, Vice CEO of Toshiba, presented a then unknown product called Digital Video Display in 1997, otherwise known as DVD's.  Through technology roadmaps, we look into the crystal ball for an outlook of technologies in 1, 5 and 10 years.  Leaders in academics such as Rao Tummala and Peter Borgeson present their leading edge research.  Come enjoy this chance to network with and learn from technology leaders from around the world!

Featured Keynote
 
Thomas Brunschwiler, research staff member of the Advanced Micro- Integration team at IBM Research - Zurich, conducts physical research and coordinates governmental and joint projects. Pushing the frontiers in 3D integration with respect to scalable heat removal and power delivery while also supporting performance and efficiency scaling of high end servers provide the focus of his current research efforts. With his Ph.D. in Electrical Engineering from the Technical University of Berlin ("Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks") Dr. Brunschwiler coordinates two European funded research projects titled HyperConnect.eu and CarrICool.eu. In addition, Thomas Brunschwiler supports the lab director of IBM Research - Zurich as a technical assistant on strategic matters. He authored and co-authored over 80 publications, two book chapters and over 50 patents in his carreer to date. A Senior Member of IEEE and on the board of the Swiss Physical Society Thomas currently serves on several technical conference committees, such as ITHERM and InterPACK.
 
Dr. Brunschwiler shares his expertise in 3D Heterogeneous Integration in his keynote on "Multi-Functional Packaging Technologies Supporting Performance and Efficiency Scaling Beyond Exa-Scale Systems" where he touches on nanotech applications for assembly, orthogonal scaling and neuromorphic computing in achieving true artificial intelligence and 'big data' handling capabilities for real world applications. His strategic perspective provides a refreshing insight into the future of computing technology and architecture.