International Wafer-Level Packaging Conference (IWLPC) Workshops
The SMTA and Chip Scale Review magazine are pleased to announce the Workshops for the 13th Annual International Wafer-Level Packaging Conference (IWLPC). On Thursday, October 20, there will be professional workshops given by instructors who are pre-eminent authorities in their fields. IWLPC will be held October 18-20, 2016 at the DoubleTree Airport Hotel in San Jose, California.
WS1: Introduction to Fan-Out Wafer-Level Packaging
Beth Keser, Ph.D., Qualcomm
Fan-Out Wafer-Level Packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking. This course has been updated with over 10% new material compared to the first time it was offered last year at IWLPC.
WS2: Wafer-Level Packaging for the Functional Integration of MEMS and ICS
Chip Spangler, Ph.D., Aspen Microsystems, LLC
The development of Wafer-Level Packaging (WLP) has been a major driving force for the size and cost reduction for integrated circuits as well as MEMS, microsystems, micro-optical and microfluidic products. Collectively referred to as MEMS, these devices require highly specialized packages that protect the fragile microstructures and still allow the desired signals, both electric and non-electric, to pass through the package to the die. The challenges and costs associated with MEMS packaging has, since the 1970’s, driven the development of Wafer-Level Packaging and associated technologies such as silicon and glass interposers, through wafer vias, wafer bonding and die stacking. Cost and size demands have since lead to the widespread adaptation of these MEMS-based WLP technologies by the integrated circuit package community. More recently the demand for multi-sensor products, greater levels of sensor intelligence and the connectivity requirements of IoT applications has driven the complex integration of MEMS and ICs through the use of WLP technologies.
WS3: Choosing the Right IC Packaging
Chet Palesko, SavanSys Solutions LLC and Jan Vardaman, TechSearch International, Inc.
In this course, we will analyze the performance and size characteristics of traditional (lead frame options, wire bond PBGA, flip chip PBGA) and advanced packaging (Wafer-Level Packaging, Fan-Out WLP options, embedded die, 2.5D/interposer-based packaging, 3D packaging with through silicon vias). For each packaging technology, this course also provides a detailed cost analysis including the manufacturing process flow to fabricate and assemble the package and the dominant technology cost drivers.
This course will also examine how OEMs and suppliers can collaborate to develop a model which optimizes product manufacturing cost for IC packages. This modeling approach has been successfully used by a number of major OEMs and suppliers in North America, Europe, and Asia to match design technology choices with supplier competencies. Yields are improved and cost reduction is achieved across the entire supply chain.
WS4: Recent Advances and New Trends in Semiconductor Packaging
John Lau, Ph.D., ASM Pacific Technology
Recent advances in, e.g., Fan-Out Wafer/Panel Level Packaging (TSMC’s InFO-WLP and IZM’s FO-PLP), 3D IC packaging (TSMC’s InFO_PoP vs. Samsung’s ePoP), through-silicon vias (TSVs), microbumps, 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU vs. Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), 3D CIS/IC integration, 3D MEMS/IC integration, thin-wafer Handling, thermal management, semiconductor and packaging for IoTs are examined, and their new trends will be discussed in this lecture. The patents impacting the semiconductor packaging the most (so far) will be mentioned first and the patent issues of Fan-Out Wafer/Panel-Level will be discussed and some recommendations will be made.
Contact Jenny Ng at 952-920-7682 or firstname.lastname@example.org with questions.
Cleaning and Conformal Coating Conference Program Finalized
The SMTA and IPC are pleased to announce the program for the 2016 Cleaning and Conformal Coating Conference being held October 25-27, 2016 in Rosemont, IL.
Two tutorials will be held on Tuesday, October 25th. Dale Lee, Plexus Corporation, will instruct “Design for Excellence: Focus on DfR-Design for Reliability of Hardware to be Cleaned” on Tuesday morning. After lunch, Doug Pauls, Rockwell Collins and Jason Keeping, P.Eng., Celestica, Inc. will co-instruct a course on “Robust Coating Processes in the Factory: Methods, Critical Parameters, Problems and Remedies.”
Session topics on October 26-27 include Processes for Achieving Reliability and Ruggedization, Cleaning Materials, Rinsing and Process Control, Conformal Coating, Customer Cleaning Challenges and Needs, Ultra-Thin or Nanocoatings in Electronics Assembly Operations.
Siva Sivasankar, Quality & Reliability Engineer at Google, will deliver the Wednesday morning keynote presentation titled “Building Reliable Hardware.” On Thursday morning, Dock Brown from DfR Solutions will deliver a keynote presentation on “Requirements for Cleaning and Coating to Building Reliable Medical Hardware.”
The Expo will be held October 26-27. Conference participants may attend the expo at no charge.
If you have any questions please contact Jenny Ng, Conference and Education Manager email@example.com
For more information or to register visit: go to www.ipc.org/cleaning
SMTA International Keynote Speaker Announced
SMTA announced the keynote speaker for the 2016 SMTA International technical conference September 25 - 29, 2016 in Rosemont, Illinois.
The Opening Session at SMTA International on September 27, 2016, will feature a keynote presentation titled “How's Your Storage?” by Daniel Kuhl, Vice President of Engineering at Seagate Technology. The presentation will provide an overview of the memory storage explosion and factors influencing global design and architecture, technology progression and infrastructure for manufacturing and validation. The data storage industry continues to be heavily driven by demanding requirements on capacity, higher performance and miniaturization while remaining sensitive to value. Daniel will share current technologies, technology enablers of the future and speak to the memory consumption rate of today and what is anticipated for the future.
Daniel has over 30 years of experience in the storage industry and holds a bachelor of science in Computer and Electrical Engineering from Purdue University, West Lafayette, Indiana. Daniel started in the HDD industry at IBM in San Jose, California and Boca Raton, Florida. In 1997, Daniel started at Seagate as a Director: Engineering Lead on the 2nd generation Enterprise 10,000 rpm HDD. In 2013 Daniel became the Vice President of Engineering, Technology Development, responsible for delivering SSD and Enterprise-class hard disk drives.
The Opening Session Keynote is a complimentary event at SMTA International open to all attendees.
For more information on SMTA International please contact SMTA Executive Administrator Tanya Martin: firstname.lastname@example.org or 952-920-7682 or visit http://www.smta.org/smtai/.
New SMTA Scholarship Rewards Student Leaders, Honors JoAnn Stromberg
The SMTA unveiled an annual scholarship for undergraduate students pursuing a degree in electronics and actively involved in the SMTA. In honor of the nearly 30 years of service dedicated by former Executive Administrator, JoAnn Stromberg, a $3000 Student Leader Scholarship was established following her retirement in 2015. The purpose of the scholarship is to encourage undergraduate students to take on more leadership opportunities and strengthen the connection between students and the electronics industry.
SMTA President Bill Barthel commented, “This scholarship is intended to pay tribute to all JoAnn has done for the Association and industry. As a former teacher this aligns with her and the Association’s values.”
Officers from the Dallas, Houston, and Austin SMTA Chapters played a critical role taking this effort from vision to reality, including criteria definition and financial support for the first five years.
More information can be found online at: http://www.smta.org/scholarship/
SMTA International 2015 Papers Now Available in SMTA Knowledge Base
The Technical Conference Proceedings from the SMTA International Conference and Exhibition (SMTAI) 2015 are now available for download from the SMTA Knowledge Base, it is announced today.
“This is your source for the latest and highest quality information and research on electronics assembly, lead-free, SMT, Package-on-Package, process control, Embedded Actives/Passives, 3D/TSV, Printed Electronics, and more,” stated Ryan Flaherty, SMTA Director of Communications, in making the announcement. “You can download more than 130 papers that were presented in the technical sessions last Fall at SMTA International, including papers from the AIMS/Harsh Environments Symposium, the Lead-Free Soldering Technology Symposium, and the Evolving Technologies Summit.”
The proceedings can be browsed directly in the online Knowledge Base here:
Featuring thousands of full-length technical articles, the SMTA Knowledge Base is searchable to all visitors, but PDF downloads are accessible for free only to SMTA members. Non-members can purchase individual articles for $10 each, or easily become an SMTA member for real-time access to the Knowledge Base.
The SMTA International Conference and Exhibition (SMTAI) 2016 will be held September 25 - 29, 2016 at the Donald Stephens Convention Center in Rosemont, IL. The SMTA International technical conferences continue the tradition of being the strongest in the electronics assembly industry.