IWLPC (Wafer-Level Packaging) Conference Proceedings


Package-On-Package Interconnect For Fan-Out Wafer Level Packages

Authors: Min Tao, Ph.D, Akash Agrawal, Ashok Prabhu, Ilyas Mohammed, Ph.D, Belgacem Haba, Ph.D
Company: Invensas Corporation
Date Published: 10/18/2016   Conference: IWLPC (Wafer-Level Packaging)


Abstract: Consumer electronics designers continue to demand thinner and lighter packages while devices increase in functional complexity. The Fan-Out Wafer Level Package (FOWLP) platform has been gaining momentum with the advantages it offers in electrical performance, assembly process efficiency and low geometric profile. Different approaches of Package-on-Package (POP) stacking in FOWLP have been developed with some approaching high volume production recently. In this paper, we will review the common configurations of stacked FOWLP with specific focus on the POP interconnects and their compatibility with the different process options. The feasibility of incorporating low cost Bonded Via Array (BVA®) [1] as one of the POP interconnect options is also discussed.

The FOWLP POP technologies available in the market fall into two main process categories: chip first, such as TSMC’s integrated Fan-Out (InFO) POP [2] and Stats Chip Pac’s encapsulated Wafer Level BGA (eWLB) [3]; and chip last, such as Amkor’s Silicon-Less Integrated Module (SLIM) and Silicon Wafer Integrated Fan-Out Technology (SWIFT) [4]. The compatibility of POP interconnect selection with the process flow, POP interconnect pitch capability, stack thickness, and potential issues of each approach will be discussed.

BVA as an POP interconnect option in FOWLP can be incorporated into either a chip first or a chip last approach. In this paper, the materials and process details describing BVA bonding onto a conventional Redistribution Layer (RDL) build up structure are discussed and the bonding feasibility is demonstrated.

Key Words: 

Fan-out Wafer Level Package, Package-On-Package Interconnect, Bonded Via Array



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