Cost: The cost is $200/$275 for SMTA members/non-members, and a one-year individual SMTA membership is included in the non-member price.
If you have questions, please contact SMTA chapter coordinator Sara Brazeau.
Course Objectives:
We will be holding two workshops, each taking up a half day.
Reducing Head in Pillow Failures
As the industry moves toward lead free soldering and Ball Grid Array packages with thinner and finer pitch, there is an increase in SMT non-wet type of defect known as head-and-pillow defect. This defect is hard to detect after SMT assembly and most likely will fail at the customer.
This training will cover the most common failure modes causing head-and-pillow in electronic assemblies. The causes of each head-and-pillow defect mode will be explained and examples of each will be detailed. It will discuss how to identify the root cause and give potential solutions to prevent the defect and have a robust SMT assembly process. Also various failure analysis techniques to identify head-and –pillow non wet will be discussed. Finally a few head-and pillow case studies will be reviewed. Topics Covered: HnP defect mechanism, Defect modes categories, Solder printing and reflow, Solder paste, Warpage, Board design, Failure analysis
The second workshop will be "Voids in Solder Joints"
Voids in solder joints have existed ever since soldering has existed dating back to biblical days. The major concern with solder voids is their potential impact on the long term reliability of the component solder joints. But, not each void is the same. There are multiple types of voids, each has unique causes, unique characteristics and varying impact on solder joint reliability. In this class, these various types of voids found in solder joints will be described. These include macro voids, also called process voids, planar microvoids, shrinkage voids, micro-via voids, and intermetallic Compound (IMC) voids. For each type, their known root causes, ways of minimizing or even eliminating them and their potential effects on solder joint reliability will be explained. Metrologies tools, such as X-ray, available to detect and measure voids, specifically in BGA solder joints, will be described. Industry specifications and guidelines for voids in solder joints will be listed.
BGA Soldering with Mixed Metallurgies Surface Mount assembly of Pb free BGA components having SnAgCu (SAC) solder balls with conventional, eutectic SnPb solder paste, also known as Backward Compatibility, has been a subject of considerable interest since the introduction of Pb free solders earlier in this decade. Most BGA package suppliers have converted their BGAs ball alloys to Pb free, using SAC solder. Some customers for these BGA packages, whose products have exemptions from the use of Pb free solders, are still employing SnPb solder paste for reflow soldering their products. This class will describe Backward Compatibility soldering for BGA components, including the various issues that may crop up when reflow soldering such components. Quality and Reliability data on mixed alloy BGA solder joints in the literature will be discussed and critical requirements for long term reliability of backward compatibility solder joints identified.
ABOUT THE INSTRUCTORS
Dudi Amir is a Senior Process Engineer for Intel Inc. based in Oregon supporting new technology development. He has participated in the development of assembly process for motherboards and mobile modules. He has also been a part of folded stacked and PoP packages development. Prior to working for Intel, Dudi was a process engineer for NEC Corporation supporting PBX and microwave board assembly. He received his Bachelor of Science in Mechanical Engineering from State University of New York at Buffalo and a Master of Science at Portland State University in Oregon. He has given many industry papers and has been awarded 9 US patents in package and board technologies.
Raiyo Aspandiar has been with Intel Corporation at the Boards and System Assembly Hillsboro, Oregon facility since 1983. He was part of the team that introduced surface mount technology to Intel. Over the years, he has participated in the development of printed circuit boards and assembly processes for motherboards and mobile modules, which contained a myriad of packages for the Intel microprocessors, chip sets and connectors. He has also been part of the Lead and Halogen Free Initiative within Intel, whose goal is to remove lead and halogens from Intel’s packaging, boards and systems products. Currently, Raiyo is working on solder voids characterization at the BGA package level, backward compatibility soldering of large, high density BGA components, and understanding Head-in-Pillow Defect Mechanisms. Raiyo has published more than 25 technical papers and is the joint holder of 15 patents in the Electronics Packaging and Manufacturing field. He is a graduate of Stanford University. He is a member of the SMTA Technical Committee and received the SMTA Member of Technical Distinction Award in 2009.
Cancellation Policy
Registration fees will be refunded if written notice is postmarked TWO WEEKS prior to the class date. "No Shows" WILL NOT be refunded in order to cover expenses incurred. If someone will be going in your place, please advise the SMTA as soon as possible.
Chapter Tutorial Programs (CTP's) are one-day technical events hosted by local chapters that feature a single instructor on a topic that is suited to that particular region.
The purpose is to address the latest information or most recent issues on a specific technology.