Español   |   中文

Chapter Tutorial Program (CTP)

CTP

Chapter Tutorial Programs (CTP's) are one-day technical events hosted by local chapters that feature a single instructor on a topic that is suited to that particular region. The purpose is to address the latest information or most recent issues on a specific technology.

Want to instruct an SMTA tutorial? View the tutorial guidelines.

Cancellation Policy: Registration fees will be refunded (less a $75 processing fee) if written notice is postmarked two weeks prior to the event date. Cancellations received within two weeks prior to event date will not be refunded to cover costs incurred.


Upcoming Chapter Tutorial Programs

March 16, 2017
LA/Orange County Chapter Tutorial Program: Design for Testability Strategies for Today's Circuits



LA/Orange County Chapter Tutorial Program: Design for Testability Strategies for Today's Circuits

Instructor: Louis Ungar, Advanced Test Engineering (A.T.E.) Solutions, Inc.

March 16, 2017
9:00 a.m. - 4:30 p.m. (8:30 a.m. Check-In)
Paradigm Contract Manufacturing LLC
11562 Knott Street, Unit 13-14
Garden Grove, CA, 92841-1823
PH - 714-889-7074
FAX - 714-893-1801
http://www.paradigmcontractmfgllc.com

Price:

Members - $200
Non-Members - $275 (A one-year Individual SMTA Membership is included in the non-member price)
LA/Orange County Chapter Officers - $100
SPECIAL OFFER! The LA/OC Chapter will subsidize the cost of registration for all student attendees.
Student Members - $FREE! (Regularly $50)
Student Non-Members - $20 (Regularly $70. A one-year Student SMTA Membership is included in the non-member price)

Great Value! Half the cost of a tutorial at SMTA International and offered right in your backyard. Lunch, coffee breaks, course handouts, and a certificate of completion are all included in the cost, along with instruction by one of our best!

Introduction:
The objective of this course is to familiarize attendees with how the testing problem should be tackled for today’s ever more complex electronic circuits. To compound the problem, access to the circuit is ever shrinking making mechanical probing more challenging and less effective. Design for Testability (DFT) techniques, including use of the JTAG/IEEE 1149.1 boundary scan helps in keeping up. The course covers issues of how to ensure that circuit boards populated with SMT devices are built correctly, but goes further to confront the question of ensuring that it in fact functions correctly. The course will cover the objectives of various test methods but will also include ways to overcome their limitations. Finally, a profitable test strategy is described and how the traditional test paradigm must change to take advantage of it.

How You Will Benefit:

  • Understand the benefits and limitations of various test equipment types
  • Learn how testing is a technical solution to an economic problem
  • Understand the modern ATE and how DFT and JTAG are now integral parts of automatic board tests
  • Learn how end users – your customers – interface with tests
  • Understand that test is an opportunity for profits, not just a cost to be avoided

    Topics Covered:
  • Strategize test as you strategize design
  • Test and repair vs. throw away: A question of economics
  • Inspectability from solder paste through fully loaded boards
  • Automatic testing and ATE test programs
  • What to expect when you test as you build and how to plan for it with Design for Testability (DFT)
  • Capitalizing JTAG/IEEE-1149.1 and other boundary scan standards for all tests
  • Tests beyond manufacturing: User built-in test, repair of field returns
  • Bottom Line:
         - What does this cost?
         - How much does it save?
         - How can we profit from better tests?

    Who should attend?
    Many people are involved in creating a product and they should be concerned that it can be proven to be good before it is sold. Quality, manufacturing, and design engineers not only need to know test to contribute to its success, but also to reap its rewards by the information tests can provide for future improvements. Managers of all disciplines need to know how tests are performed and how to benefit from them rather than simplistically aim only to lower test costs. Finally, test engineers need this course so they can communicate their concerns with others in the organization.

    Louis Ungar About the Instructor:
    Louis Ungar
    Mr. Ungar enjoys a well-known reputation in the electronics testing profession. He has built, programmed, and selected Automatic Test Equipment (ATE) for a large number of clients both in the commercial and military community. Having introduced the first university course on ATE and Design for Testability (DFT) at UCLA, he has taught similar courses to companies around the world. He led the Surface Mount Technology Association (SMTA) Testability Committee to publish the SMTA Testability Guidelines from 2002 with the most recent 2014 SMTA Testability Guidelines. He has been involved with the IEEE standards committee for several DFT standards, including the IEEE-1149.1, the 1149.4 and the 1687 and has been honored as a life-time member of the American Society of Test Engineers and is the Tutorial Chair of the IEEE AutoTestCon. He is involved with the IPC-2231 standard for DFX, where X is substituted for Testability, Reliability, Manufacturability, etc. He is also the co-author of a technical paper on False Alarms and No Fault Found that won the Best Management Paper award at AutoTestCon 2015. Mr. Ungar completed courses towards a MA in Management and holds a BS degree in Electronics Engineering and Computer Sciences from UCLA. He continues teaching DFT and BIST courses at conferences, at companies and at public forums around the world.


    Contact Karen Frericks at 952.920.7682 with questions.

  • Registrations are being taken through the SMTA Online Registration System.