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Jasbir shares his perspective of tech sessions.
Sessions are 1.5 hour programs in which three technical papers are presented under the direction of a chairman. Each paper is presented by the author on a topic related to the main subject of the session, and is followed by audience questions. The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers. Organized by track, and by day within each track.

The objective of a technical session is to bring new scientific and technical developments to light. Emphasis is placed on original, previously unpublished papers.

Monday
  • 8:00 – 9:30am
  • 10:00am – 12:00pm
  • 12:00 – 1:30pm
  • 1:30 – 3:00pm
  • 3:30 – 5:00pm
    •      		Tuesday
  • 10:30am – 12:30pm
  • 2:00 – 3:30pm
  • 4:00 – 5:30pm
    •      		Wednesday
  • 8:00 – 9:30am
  • 10:30am – 12:00pm
  • 2:00 - 3:30pm
  • 4:00 - 5:30pm
    •      		Thursday
  • 8:00 – 9:30am
  • 10:00 – 11:30am
  • 1:00 – 2:30pm
  • 3:00 – 4:30pm
    •


    Please note that speakers with a Speaker of Distinction icon are recognized as Speakers of Distinction. Over the past 15 years they have been identified by SMTAI attendees as giving the strongest technical presentations. Congratulations to each of these authors for a job exceptionally well done.



    MONDAY, OCTOBER 25
    8:00am – 9:30am


     ET1 MEMS and Image Sensor Assembly Processing and Reliability
    Chair: Steve Greathouse, Plexus Corporation
    Co-Chair: Lars Böttcher, Fraunhofer IZM
    Monday, October 25
    8:00am–9:30am, Asia 1

    Micro Electrical Mechanical Systems (MEMS) are finding their way into almost all phases of life. As the population grows and matures, society is demanding better and much more cost effective diagnostic products to improve long-term health and well being. For many MEMS technologies to function, the package needs to have access and interact with the environment. This can present numerous challenges in the design and manufacturing process. You will be missing a great MEMS session if you don’t attend!

  • The Encapsulation of MEMS/Sensors on Package Level and Wafer Level With Film Assisted Molding Technology
    Ton van Weelden and Lingen Wang, Boschman Technologies B.V.
  • Reliability Testing of Linear Image Sensor Devices
    Awni Qasaimeh, Mridula Gosavi, Susan Lu, and Bahgat Sammakia, Binghamton University; Mike Joyner, Mike Sullivan, and Jeff Zarnowski, Panavision Imaging, LLC
  • Biocompatible Polymer Composite Material for Highly Sensitive Point of Care BioMEMS Microcantilever Sensors
    Arvind Sai Sarathi Vasan, Ravi Doraiswami, Ph.D., and Michael Pecht, Ph.D., Center for Advanced Life Cycle Engineering (CALCE), University of Maryland; Michael Pecht, Ph.D. City University of Hong Kong



    HE1 Pb-Free Technology Insertion
    Chair: John Evans, Ph.D., Auburn University
    Co-Chair: Heather McCormick, Celestica Inc.
    Monday, October 25
    8:00am – 9:30am, Oceanic 7

  • The Pb-Free in Electronics Risk Mitigation (PERM) Consortium
    Anthony J. Rafanelli, Ph.D., P.E., Raytheon Integrated Defense Systems
  • Overview of New DoD Reliability Revitalization Initiatives
    James G. McLeish, CRE, DfR Solutions



    MONDAY, OCTOBER 25
    10:00am – 12:00pm


     ET2 Advanced Packages and Processes
    Chair: Andrew Perkins, Ph.D., Aptina Imaging
    Co-Chair: Brian Roggeman, Universal Instruments
    Monday, October 25
    10:00am – 12:00pm, Asia 1

    Advancements in packaging processes are needed for products with exotic semiconductor materials, nanocomposite materials, through silicon vias, and multiple components. This session presents wafer edge protection during TSV formation as well as package considerations for CZT detectors, RF MMIC devices, and microfabricated neural electrode arrays made from a variable-modulus nanocomposite material. Insight will be gained as to how conventional packaging processes like die handling and wirebonding can be modified for new packaging requirements.

  • A Cost Effective Process for Edge Protection of Wafers and Fabrication of Through-Silicon Vias Using Wet Etching of Silicon
    Ramachandran K. Trichur, Gary J. Brand, Curtis Planje, and Xie Shao, Brewer Science, Inc.
  • Challenges of Packaging Cd-Zn-Te (CZT) Detectors
    Charles G. Woychik, Ph.D., (presently at Tessera; Inc.); Brian D. Yanoff, Ph.D., James E. Simpson, Ph.D., Jay Cao, Ph.D., Ian M. Spinelli, and Vincent S. Smetkowski, Ph.D., GE Global Research; James Adriance, Lawrence Harvilchuck, Brian Roggeman, and George Westby, Universal Instruments Corporation
  • Overcoming Complex Manufacturing Issues With RF MMIC Products: A Case Study
    Steve Greathouse, Jennifer Davisson, Gary Catlin, Jared Stockett, Teri Whipple, Richard Garcia, Steve Abrahamson, and Jim Spinuzzi, Plexus Corporation, Microelectronics Product Group
  • Development of a Packaging System for Clinical Evaluation of a Nanocomposite-Based Neural Electrode Array Fabricated from a Chemoresponsive Polymer Substrate
    Andrew Barnes, Allison Hess, and Christian Zorman, Case Western Reserve University; Mondhita Diewvilai, Chulalongkorn University



    HE2 Component Packaging Challenges in Harsh Environments
    Chair: Salvatore Rampaul-Pino, Vision Research
    Co-Chair: Larry Wang, Lord Corporation
    Monday, October 25
    10:00am – 12:00pm, Oceanic 7

  • High Temperature Electronics Packaging Technology for Signal Conditioning and Processing Circuits
    S.T. Riches, GE Aviation Systems; C. Johnston, M. Sousa, P. Grant, and D. Shepherd, Oxford University Materials Department
  • Resistance of Common PWB Surface Finishes Against Corrosion in Harsh Environments
    Mustafa Özkök, Mario Gensicke, and Guenter Heinz, Atotech Deutschland GmbH, Hugh Roberts and Joe McGurran, Atotech USA Inc.
  • Harsh Environment Impact on Resistor Reliability
    Marie Cole, Lenas Hedlund, George Hutt, Tibor Kiraly, Levente Klein, Steve Nickel, Prabjit Singh, and Tim Tofil, IBM Corporation



    MONDAY, OCTOBER 25
    12:00pm – 1:30pm


     Evolving Technologies Keynote Lunch
    Reading the Fine Print: Challenges and Outlook for Printed Electronics
    Charles E. Bauer, Ph.D. and Herbert J. Neuhaus, Ph.D., TechLead Corporation
    Chair: Reza Ghaffarian, Ph.D., Jet Propulsion Laboratory
    Monday, October 25
    12:00pm – 1:30pm, Asia 1



    Harsh Environments Keynote Lunch
    The Tech in Green Tech
    Irene Sterian, Celestica Inc.
    Chair: John Evans, Ph.D., Auburn University
    Co-Chair: Heather McCormick, Celestica Inc.
    Monday, October 25
    12:00pm – 1:30pm, Oceanic 7



    MONDAY, OCTOBER 25
    1:30pm – 3:00pm


     ET3 Printed Electronics: Solar, Lighting, Batteries, Etc.
    Chair: Alexander Zeitler, Soligie, Inc.
    Co-Chair: Jeff Kennedy, Celestica Inc.
    Monday, October 25
    1:30pm – 3:00pm, Asia 1

    Printed electronics is a new and emerging technology which uses conductive, semi-conductive, and dielectric inks printed with a multitude of methods on paper and plastic film substrates to produce mass production of products. This session will discuss the market of printed electronics trends and barriers, OLED construction and production methods, and all processes and materials that make-up the industry. After this session, you will leave with a good understanding of what it is about and a high level understanding of what it takes to build these products.

  • Organic and Printed Electronics-A View From the Traditional Marketplace
    David Baron, Frank Bruening, Ph.D., and Robin Taylor, Atotech Deutschland GmbH
  • Printed Electronics for Flexible Solid State Lighting
    Marc Chason, Marc Chason and Associates, Inc.
  • Applications Methods and Material Sets for Printed Electronics
    Daniel Fenner, Henkel Corporation



    HE3 Organic Materials Adapted for Harsh Environments
    Chair: Larry Wang, Lord Corporation
    Co-Chair: Salvatore Rampaul-Pino, Vision Research
    Monday, October 25
    1:30pm – 3:00pm, Oceanic 7

  • Harsh Environments and Volatiles in Sealed Enclosures
    Robert K. Lowry, Consultant, Electronic Materials; Richard C. Kullberg, Vacuum Energy, Inc.; and Daniel J. Rossiter, Oneida Research Services
  • An Evaluation of Sealants Used in Photovoltaic (PV) Module Manufacture
    Jasbir Bath, Mike Moreau, and Martin Gershenson, Christopher Associates Inc.; Cathy He, Yinbai Li, and Miaosheng Zheng, Beijing Tonsan Adhesive Co. Ltd.



    MONDAY, OCTOBER 25
    3:30pm – 5:00pm


     ET4 Evolving Technology and Current Issues Panel - FREE Beer and Pretzels!
    Chair: Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory
    Co-Chair: Jeff Kennedy, Celestica Inc.
    Monday, October 25
    3:30pm – 5:00pm, Asia 1

    Come and join the team of industry experts to learn where the technology is heading and the current key issues in packaging, surface mount materials and manufacturing. Experts from industry will first present an overview of current and future technology, current status of solar and the SMT relationship, as well as a special presentation on challenges of embedded capacitors. Bring your challenging issues/questions from work to get answers from experts who provide unique perspectives based on their experience.

  • New Challenges and Developments in Discrete and Embedded Capacitors
    Alan Rae, Ph.D., TPF Enterprises LLC

    Panelists will include:
  • Lars Böttcher, Fraunhofer IZM, (Advanced Packaging in Europe)
  • Ken Gilleo, Ph.D., ET-Trends LLC, (The Next Generation)
  • Steve Greathouse, Plexus Corporation, (New/Evolving Technologies)
  • Alan Rae, Ph.D., TPF Enterprises LLC, (Nano Materials and Embedded Technology)
  • Irene Sterian, Celestica Inc., (Solar Energy and SMT)
  • Charles Woychik, Ph.D., Tessera (Advanced Packaging)



    HE4 Interconnection Reliability
    Chair: Heather McCormick, Celestica Inc.
    Co-Chair: John Evans, Ph.D., Auburn University
    Monday, October 25
    3:00pm – 5:00pm, Oceanic 7

  • Ball Grid Array Component Failure Analysis for High Reliability Electronic Systems
    J. Scott Nelson, Harris Corporation
  • High Reliability Bond Pads
    Terence Collier, Bal Benavidez, and Indira Gubeljic, CVInc
  • Interrogation of Damage-State in Lead-Free Electronics Under Sequential Exposure to Thermal Aging and Thermal Cycling
    Pradeep Lall, Rahul Vaidya, and Vikrant More, Auburn University; Kai Goebel, NASA Ames Research Center



    TUESDAY, OCTOBER 26
    10:00am – 12:30pm


     AAT1 Package on Package Assembly Optimization
    Chair: Randy Schueller, Ph.D., DfR Solutions
    Co-Chair: Andrew Mawer, Freescale Semiconductor
    Tuesday, October 26, 10:30am – 12:30pm, Asia 1

    Package on package (PoP) has become a popular packaging strategy for increasing density and performance of electronic assemblies. However, with this new technology comes assembly challenges. The papers in this session will provide results of studies to determine the best solder fluxes and paste materials needed for assembling the packages together (using dip transfer). The final paper goes further and shares the results from a detailed DOE revealing the best oven parameters to use in assembling the final PoP to the board (along with drop and thermal shock test results). If you are involved in PoP assembly these papers will be extremely valuable.

  • An Investigation into the Development of Lead-Free Solder Paste for Package on Package (PoP) Component Manufacturing Applications
    Jasbir BathSpeaker of Distinction, Manabu Itoh, Gordon Clark, Masatoshi Fuji, and Hajime Takahashi, Koki Company Limited; Jasbir BathSpeaker of Distinction and Roberto Garcia, Christopher Associates Inc.
  • Selection of Dip Transfer Fluxes and Solder Pastes for PoP Assembly
    Yan Liu, Ph.D., Pamela Fiacco, Derrick Herron, and Ning-Cheng Lee, Ph.D.Speaker of Distinction, Indium Corporation
  • Surface Mount Performance of 0.4mm-Pitch Solder Joints With Focus on Stacking Materials and Processes for Package-on-Package Applications
    Jason Brand, Myung Jin Yim, Nanette Quevedo, Maria Ospina, Ravikumar Adimula, and Cenon Dayawon, Micron Technology, Inc.
  • Analysis of the Influence of Reflow Profile Parameters on Package on Package (PoP) Component Assembly
    Rangaraj Dhanasekaran, Harish Gadepalli, and S. Manian Ramkumar, Ph.D.Speaker of Distinction, Rochester Institute of Technology



    SMT1 Advances in Stencil Technologies for Fine/Ultrafine Pitch Printing
    Chair: Joseph Belmonte, ITM Consulting/Creyr Innovation
    Co-Chair: Denis Barbini, Ph.D.
    Tuesday, October 26, 10:30am – 12:30pm, Asia 2

    Achieving the appropriate area ratios and wall finishes is very critical in the design and manufacture of stencils for smaller passive devices and fine/ultrafine pitch area array packaging. This session will provide findings from the perspective of a stencil manufacturer, an end user and academia. The session will highlight the stencil materials, manufacturing and aperture coating methods to provide good paste transfer efficiency.

  • Stencil Enabling Processes for Small Area Ratio's
    William E. Coleman, Ph.D., Photo Stencil
  • Stencil Performance Comparison
    Richard Lieske, DEK
  • Stencil Technologies for Small Aperture Printing
    Kevin Liticker, MS, CSSBB, Rockwell Automation
  • Characteristics and Potentials of Nano-Coated Stencils for Stencil Printing Optimization
    Michael Rösch and Jörg Franke, Institute FAPS, University of Erlangen-Nuremberg; Carmina Läntzsch and Georg Kleemann, LaserJob GmbH



    MFX1 Conformal Coating for Today's Electronics Industry
    Chair: Jason Keeping, P.E., Celestica Inc.
    Co-Chair: Mike Nadreau, Henkel Corporation
    Tuesday, October 26, 10:30am – 12:30pm, Oceanic 3

    Conformal Coating (CC) has been the most prominent surface protection finish within the Electronics Manufacturing Systems (EMS) Industry for many years, including the initial years of pin-through-hole technology. With increased environmental knowledge and legislation in the 20th century to better our well being, Conformal Coating materials were also required to be modified. Thus, new environmental friendly blends of coatings and processes have evolved.

  • How to Deal With Problem Areas for Selective Conformal Coating
    Arjen Koppens and Ad van Dinter, DIMA Dispense Technology and DIMA Group B.V.
  • Moisture-Cure Polyurethanes – Latest Developments in VOC-free Conformal Coatings
    Jade P. Bridges, Electrolube Ltd.
  • Ultraviolet Conformal Coating Process Development
    Corey Peterson, Rockwell Automation
  • Environment-Friendly Vapor Phase Conformal Insulation Options for Reliability Improvement of Electronics
    Rakesh Kumar, Specialty Coating Systems



    DCA1 New Approach to Solder Bumping and Optimization of Si-on-Si Assembly
    Chair: Charles Woychik, Ph.D., Tessera, Inc.
    Co-Chair: Anurag Bansal, Ph.D., Cisco Systems, Inc.
    Tuesday, October 26, 10:30am – 11:30am, Oceanic 8

    A Polyimide over UBM, also known as POU, is a new bump structure where the polyimide sits on top of the UBM. This design can be used to reduce the mechanical stress in the solder bump. A new process has been developed to do a plated POU bump. A Design of Experiment (DOE) methodology was used to optimize a Pb-free flip chip assembly process for 3D chip stacking. Reliability test data will be presented to support the optimized process conditions.

  • Polyimide-Over-UBM Process: The Challenges and Solutions on Plating Bump Process
    Roden Topacio, AMD, Inc.
  • Pb-Free Reflow Profile Process Study for High Yield, High Reliability Flip Chip on Silicon Substrate Assembly
    Zhaozhi Li and John L. Evans, Auburn University; Sangil Lee and Daniel F. Baldwin,, Georgia Institute of Technology; Brian J. Lewis and Paul N. Houston, ENGENT, Inc.; Gene Stout and Ted Tessier, Flip Chip International LLC



    Free Lunch in the Exhibit Hall on Tuesday Free Lunch!
    Everyone is welcome to join us 12-2pm on Tuesday (October 26) for a free lunch on the show floor.



    TUESDAY, OCTOBER 26
    2:00pm – 3:30pm


     AAT2 Mechanical and Electrical Characterization of Package on Package Systems
    Chair: Sheldon Schwandt, Research In Motion
    Co-Chair: Heather McCormick, Celestica Inc.
    Tuesday, October 26, 2:00pm – 3:30pm, Asia 1

    The proliferation of PoP systems in electronics has continued to grow dramatically in 2010 and the wealth of data collected for discrete systems needs to be collected for Package on Package systems. The impact of material selection, such as solder alloys, plays a large role in the overall system reliability and the collection of critical data is needed to help optimize solutions for future use in everything from consumer electronics to military.

  • Temperature Cycling of Pb-free and Mixed Solder Interconnections Used on a Package-on-Package Test Vehicle
    P. T. ViancoSpeaker of Distinction, J. M. Grazier, J. A. Rejent, and A. C. Kilgo, Sandia National Laboratories; F. Verdi and C. Meola, ACI Technologies, Inc.
  • Characterization of Thermal-electrical and Mechanical Behaviour of PoP
    K. Weide-Zaage and L. Meinshausen, Information Technology Laboratory, Leibniz University Hannover; H. Frémont, Laboratoire IMS, Université Bordeaux I
  • Thermal Cycling Reliability of Package on Packages Assembled by One-Pass and Two-Pass Techniques
    Nicholas Williard, Preeti Chauhan, Vikram Srinivas, Michael Osterman, and Michael Pecht, CALCE Electronic Products and Systems Center, University of Maryland; Robert Farrell, Benchmark Electronics, Inc.



    SMT2 Cleaning for Today's Challenging Designs Sexton: pls remove yellow…
    Chair: Linda Woody, Lockheed Martin
    Co-Chair: Laura Turbini, Ph.D., Research In Motion
    Tuesday, October 26 2:00pm – 4:00pm, Asia 2

    Emerging package technology is driving electronics to smaller more dense circuit cards. This trend to very high density low standoff parts is causing great concern for those required to remove all flux residues. This session will explore the compatibility of the new flux chemistries with the available cleaning chemistries, investigate the requirements for the new low standoff packages, and finally compare the different cleaning equipment technologies available today.

  • Benchmark Study: pH-Neutral vs. Alkaline Cleaning Agents
    Harald Wack, Ph.D. and Umut Tosun, ZESTRON America; John Neidermann, Speedline Technologies; and John Radmann, Trace Laboratories
  • Issues and Concerns in Cleaning Under Low Profile Components
    Rich Brooks and Mike Bixenman, D.B.A., Kyzen Corporation
  • Big Cleaning Job vs. Small Cleaners: The Advantages and Pitfalls of Going Small
    Eric Camden, Foresite, Inc.
  • Clean "No-Clean" or Use a Water Wash Solder Paste?
    Gerjan Diepstraten, Cobar Europe B.V. and Tim Lawrence, Ph.D., Cobar/Balver Zinn



    MFX2 Alternate Lead-Free Alloys: Materials and Processes
    Chair: Ron Lasky, Ph.D., P.E., Indium Corporation
    Co-Chair: Phil Zarrow, ITM Consulting
    Tuesday, October 26, 2:00pm – 3:30pm, Oceanic 3

    For a few years it appeared that the electronics assembly industry might settle on SAC305 as the alloy of choice for SMT lead-free assembly. More recent developments have established that SAC105 provides improved drop shock performance. Earlier work had shown that small quantities of dopants dramatically improved the performance of SnCu wave solder alloys. The confluence of these and other findings have resulted in considerable new work on alternate lead-free alloys. In addition, mixed alloy systems (leaded and lead-free solders) still pose many challenges. The papers in this session will address some of these issues.

  • Low-Silver BGA Assembly, Phase 2- Reliability Assessment, Sixth Report: Thermal Cycling Results for Unlimited Joints
    Gregory HenshallSpeaker of Distinction and Michael Fehrenbach, Hewlett-Packard Company; Chrys SheaSpeaker of Distinction, Shea Engineering Services; Quyen Chu and Girish Wable, Jabil Circuit; Ranjit Pandher, Cookson Electronics; Ken Hubbard and Gnyaneshwar Ramakrishna, Cisco Systems; and Ahmer SyedSpeaker of Distinction, Amkor Technology
  • The Development of an Improved Tin-Zinc Solder
    Keith Sweatman, Takashi Nozu, and Tetsuro Nishimura, Nihon Superior Co. Ltd.
  • The Effect of Silver Content on the Solder Joint Reliability of a Pb-free PBGA Package
    Richard CoyleSpeaker of Distinction, Peter Read, Richard Popowich, and Debra Fleming, Alcatel-Lucent; Heather McCormickSpeaker of Distinction, Celestica Inc.; John Osenbach, LSI Corporation; John Manock, formerly Alcatel-Lucent



    DCA2 New Applications and Processes
    Chair: Don Banks, St. Jude Medical
    Co-Chair: Lars Böttcher, Fraunhofer IZM
    Tuesday, October 26, 2:00pm – 3:30pm, Oceanic 8

    As flip chip devices gain more market acceptance, technology advances continue. The design and assembly challenges of capacitive micro-machined ultrasound transducers (cMUTs) attached to organic carriers are presented. Next is a discussion of embedded actives and passives in which components are moved from the surface into the build-up layers of laminate substrates. New vialess processing is covered. Last is a non-local two-dimensional model to evaluate interfacial thermal stresses and deformation in Pb-free flip chip ball grid array.

  • Packaging High Density Capacitive Micro-Machined Ultrasonic Transducers (cMUT) Sensor Arrays Using HyperBGA® Technology – Part II
    Robert Wodnicki, Charles G. Woychik, and Kai Thomenius, GE Global Research; Glen Thomas, Irv Memis, Ulises Penaherrera, Barry Bonitz, and Todd Davies, Endicott Interconnect Technologies, Inc.; Charles G. Woychik, (currently at) Tessera Inc.
  • Next Generation System in a Package Manufacturing
    Lars BoettcherSpeaker of Distinction and Andreas Ostmann, Fraunhofer Institute for Reliability and Microintegration (IZM); Dionysios Manessis, Stefan Karaszkiewicz, and Herbert Reichl, Technical University of Berlin
  • Thermal Warpage of Flip-Chip Plastic Ball Grid Array Component: Experiment and Modeling
    A. Shirazi, H. Lu, and A. Varvani-Farahani, Department of Mechanical Engineering, Ryerson University



    EMS1 Outsourcing Strategies: Niche Requirements and EMS Best Practices
    Chair: Mike Buetow, CIRCUITS ASSEMBLY Magazine
    Co-Chair: Sue Mucha, Powell-Mucha Consulting, Inc.
    Tuesday, October 26, 2:00pm – 3:30pm, Europe 1

    Determining whether to outsource is sometimes the simplest part of the decision tree. Deciding where and with whom to outsource is often what determines success or failure. Two of this session's presentations will help shape the OEM buyer's or engineer's approach to choosing the best fit for their product and service requirements. Meanwhile, the final paper looks at the equation from the OEM's perspective, outlining just what makes a best-in-class EMS company for a high-growth market.

  • ODM or EMS: Which Choice is Best for Your Project?
    Jim Chen, Tailyn Communication Company, Ltd. 
  • How Efficient Is Your High Mix EMS Supplier
    Dave Cesar, The Parkland Group and Roy Starks, Libra Industries
  • Outsourcing LED PCB Manufacture
    Scott Mauldin, LEDnovation, Inc.



    TUESDAY, OCTOBER 26
    4:00pm – 5:30pm


     AAT3 Assembly Challenges With BGA/LGA
    Chair: Andrew Mawer, Freescale Semiconductor
    Co-Chair: Ken Gilleo, Ph.D., ET-Trends LLC
    Tuesday, October 26, 4:00pm – 5:30pm, Asia 1

    This session will cover some common issues being experienced with the surface mount assembly of BGA and LGA components. The first paper outlines some of the unique challenges associated with using LGA components and provides solutions to overcome them. The second presentation goes over many of the factors that can contribute to one of the most common BGA SMT defects being experienced today, Head in Pillow or HiP. The last paper covers the assembly reliability of a large BGA with two different alloys of Pb-free spheres assembled with SnPb solder paste.

  • Land and Solder Grid Array SMT Assembly Challenges
    Dudi Amir, Intel Corporation
  • Head-in-Pillow: Alarm Still Ringing? A Continuation Study on Known Chemical and Mechanical Factors in BGA Non-Wet
    Masato Shimamura and Tomoko Nonaka, Senju Metal Industry Co., Ltd.; Tetsuya Okuno, Satoru Akita, and Derek Daily, Senju Comtek Corporation
  • A Reliability Comparison of SAC305 and SAC105 Plastic Ball Grid Arrays Assembled with Backward Compatible Soldering Processes
    Richard CoyleSpeaker of Distinction, Peter Read, Richard Popowich, and Debra Fleming, Alcatel-Lucent; Heather McCormickSpeaker of Distinction, Celestica Inc.; John Osenbach, LSI Corporation



    SMT3 Cleanliness Measurement and Monitoring Issues
    Chair: Dale Lee, Plexus Corporation Technology Group
    Co-Chair: Mumtaz Bora, Peregrine Semiconductor
    Tuesday, October 26, 4:00pm – 5:30pm, Asia 2

    The first documented issue of cleanliness in electrical assemblies was in 1947 by Grace Murray with the identification of a moth trapped between points on a relay (#70, Panel F) of the Mark II Aiken Relay Calculator (a primitive computer). This instance not only documents the importance of cleanliness in assemblies but the importance of location. With the advent of through component mass soldering processes in the seventies, the one side of the entire assembly was covered with mostly organic based fluxes in an alcohol based liquid. Cleanliness measurement systems were developed based on these conditions. However, with today's electronic assemblies, flux chemistries are only applied only to localized areas that require solder with fluxes that may be "VOC" free.

    It is not the lack of cleanliness of the entire board which causes the electrical failure but the lack of cleanliness between two pads of a critical circuit. This session will address cleanliness measurement/ monitoring issues with what should be measured that would impact reliability and methods for measurement of these elements.

  • How Clean is Clean
    Graham Naisbitt, Gen3 Systems Ltd.
  • Ionic Contamination Extraction Effectiveness and Correlation of Analysis Methods
    Pravin Sequeira, Kantesh Doss, Arnold Hogrefe, and Minh Nguyen, Jabil
  • Validation of a New "R.OS.E." Cleanliness Test Method
    Curtis Hart, Hart Engineering; Steve Stach, Austin American Technology; and Mike Bixenman, DBA, Kyzen Corporation



    MFX3 High Speed Connector Attachment Technology
    Chair: Jim Zanolli, TEKA Interconnection Systems
    Co-Chair: Heather McCormick, Celestica Inc.
    Tuesday, October 26, 4:00pm – 5:30pm, Oceanic 3

    Increasing customer requirements for performance, density and reliability are creating challenges for the design and manufacturing of connectors as well as PCB assembly, rework and reflow processing. This session will address these areas with specific emphasis on connector area array and press-fit technologies.

  • Press-fit Interconnection Assembly Challenges and Solutions
    Phil Isaacs and Sven Peng, IBM Corporation; HM Chan, Wai Mun Lee, and Alex Chen, Celestica Inc.
  • Long-Term Reliability Assessment of a New Lead-Free Area Array Connector System
    Takeshi Saito and Nobuhiro Tamai, Hirose Electric, Inc.; Takashi Kikuchi, Hirose Electric USA, Inc.; Gnyaneshwar Ramakrishna, Cisco Systems, Inc.; Chrys Shea, Shea Engineering Services; Jean-Paul Clech, EPSI, Inc.
  • New Solder Attach in Area Array Connector: Assessing the Reliability of Solder Charge SMT Assembly
    Theeraphong Kanjanupathum and Teng Hoon Ng, Celestica Inc.; Adam Stanczak, Molex



    EMS2 EMS Segment Focus: Aerospace/Defense
    Chair: Sue Mucha, Powell-Mucha Consulting, Inc.
    Co-Chair: Mike Buetow, CIRCUITS ASSEMBLY Magazine
    Tuesday, October 26, 4:00pm – 5:30pm, Europe 1

  • Understanding Differences Between Defense OEM/CEM and Traditional CEM Business Models
    Allan B. Day, TEAM Technologies, Inc.
  • ITAR Compliance – Challenges and Benefits in an Outsourced Relationship
    Joe O'Neill, Hunter Technology Corporation
  • Practical Issues and Solutions for Handling Plastic Encapsulated Microcircuits (PEMs)
    Rick Iodice, Raytheon Integrated Defense Systems



    BUS1 Managing the Escalating Indirect Material Costs for High-Reliability Applications
    Chair: Gary Tanel, Circuitronics Inc.
    Co-Chair: Jim Baker, Spectra Sales Corporation
    Tuesday, October 26, 4:00pm – 5:30pm, Oceanic 8

    Parts are becoming obsolete far before the end of the product life. This session will discuss ways to deal with this reality. The aerospace, medical, and military markets are being hit hard by the reduction of SN/Pb solder; forcing them to take extraordinary means to ensure component availability through the life of the product. The supply chain is being driven by the high volume RoHS marketplace and increasing the availability gap for the lower volume products. Managing the Life-Time-Buys and counterfeit parts is forcing the system price upward to the point where it is setting the value of the system being manufactured. This session is directed to fit the needs of the supply chain managers and product designers in the high-reliability marketplace.

  • Bridging Supply Chain Gap for Exempt High-Reliability "OEM's" Tin Whisker Mitigation and Counterfeit Detection
    Nicholas Leonardi, Premier Semiconductor Services
  • Moisture and Contamination Considerations for Long Term Storage of End of Life Electronic Components
    Lee Melatti, Channel One International
  • Electronic Product Assembly in the Global Marketplace: The Material Piece of the Competitive Puzzle
    Tom Borkes, The Jefferson Project



    WEDNESDAY, OCTOBER 27
    8:00am – 9:30am


     AAT4 Assembly of Bottom Termination Components
    Chair: Lee Smith, Amkor Technology
    Co-Chair: Hugh Roberts, Atotech USA
    Wednesday, October 27, 8:00am – 9:30am, Asia 1

    This session covers various issues related to solderability and assembly of bottom termination packages to the board. This includes the effect of lead termination finish on solderability, assembly of QFN packages using process parameters optimized for mixed and high thermal mass components, and room temperature bonding of D-Pack components for LED applications.

  • Quad Flat No Lead (QFN) Package Processing in High Thermal Mass Assembly
    Jinda Songninluck, Theeraphong Kanjanupathum, and Teng Hoon Ng, Celestica Technology Development
  • NiPdAu Plating Qualification of RF-IC Packages
    Mumtaz Y. Bora, Peregrine Semiconductor
  • Room Temperature LED and D-Pack Type Component-Attach and Reliability Testing
    T. Acchione and M. Scalzo, Indium Corporation



    SMT4 Conquering Broadband Stencil Printing Challenges
    Chair: Jeff Schake, DEK USA
    Co-Chair: Denis Jean, Plexus Corporation
    Wednesday, October 27, 8:00am – 9:30am, Asia 2

    Following the conventional evolution of stencil printing, stencil aperture dimensions must scale smaller to fit shrinking component dimensions. However, this increases the challenge of satisfying aperture area ratio guidelines using uniform thickness stencils to balance solder volume requirements against a broadening range of component sizes. Progress to expand the solder printing process window via innovations in machine, stencil, and solder paste will be presented.

  • New Developments in Broadband Printing Techniques
    Mark Whitmore and Clive AshmoreSpeaker of Distinction, DEK Printing Machines Ltd.
  • Evaluation of Nano-Coated Stencil for Ultra Fine Pitch Component Assembly
    Rita Mohanty, Ph.D., and Rajiv Iyer, Speedline Technologies; Sharan Hoogar and Daryl Santos, Ph.D., Binghamton University
  • Specification Limits Review for Solder Paste Stencil Print Inspection (SPI)
    David Sbiroli, Ed Briggs, and Chris Anglin, Indium Corporation



    MFX4 Lead-Free Wave Soldering Process for Today's Challenges
    Chair: Ursula Marquez de Tino, Ph.D., Plexus Corporation
    Co-Chair: Chris Nash, Indium Corporation
    Wednesday, October 27, 8:00am – 9:30am, Oceanic 3

    Thick, complex Printed Circuit Boards using lead-free wave soldering processes creates many challenges for the board assembler. Various process, design, and material parameters can be optimized to overcome difficulties during assembly. An optimized assembly will result also on higher reliability of through holes and SMD components.

  • Lead-Free Wave Soldering for Process and Product Design Improvement in SnCu Alloys
    Juthathip Fangkangwanwong, Mongkhol Phuhattsuan, and Teng Hoon Ng, Celestica Co. Ltd.
  • Challenges in Lead-Free Wave Soldering
    Sunil Gopakumar, Francois Billaut, and Eric Fremd, Brocade Communications; Chris Chu, K. Y. Tsai, Chu Lin, and Toyma Lee, Foxconn; Jasbir BathSpeaker of Distinction, Bath Technical Consultancy
  • iNEMI Lead-Free Wave Soldering Project: An Investigation of Reliability of Through-Hole Electrical Interconnects
    Denis Barbini, Ph.D., BCS; Denis Jean, Plexus Corporation; Stuart Longgood, Delphi Corporation; Keith Howell, Nihon Superior Co. Ltd.; Jian Miremadi, Hewlett-Packard Company



    PRC1 Using Automated Optical Inspection (AOI) and Automated X-Ray Inspection (AXI) to Reduce Cost Through Process Capability and Control
    Chair: Tom Borkes, The Jefferson Project
    Co-Chair: Rod Howell, Libra Industries
    Wednesday, October 27, 8:00am – 9:30am, Europe 1

    Having capable and controllable assembly processes are essential elements that characterize successful electronic manufacturing companies. An assembly infrastructure that takes advantage of today's automated inspection technologies assists in the goal of achieving best-in-class yields, as well as, significantly reducing the labor costs associated with manual inspection. The key to process control is not to use these automated inspection tools reactively, but to use them proactively in real time. What role can AOI and AXI play in achieving these quality assurance objectives? Does one need both? If only one, which one?

  • Comparison of Various Metrologies to Measure Voids in X-Ray Images of High Density BGA Package Solder Balls
    Ife Hsu and Raiyo Aspandiar, Ph.D., Intel Corporation; and contributions from JEDEC Task Group: Sherstin Mortensen, Intel Corporation; Christine Blair, ST Micro; Dong Ming, Freescale Semiconductor; Keith Newman, Oracle Corporation; Isabel de SousaSpeaker of Distinction, IBM; and Patrick Thompson, Texas Instruments
  • AOI in an 01005 World
    Galen Alexander, Cathy Combet, and Ming-Ming Chang, Vi Technology



    SUB1 Environmental Factors Influencing PCB Creep Corrosion and Mitigation Steps to Prevent It
    Chair: Lenora Toscano, MacDermid, Inc.
    Co-Chair: Anil Kurella, Ph.D., Intel Corporation
    Wednesday, October 27, 8:00am – 9:30am, Oceanic 5

    Electronics are seeing increasingly harsh environments as a result of environmental pollution. This session investigates the environmental influencing factors of creep corrosion. How to recreate them and mitigation steps to reduce the corrosion found on PCBs exposed to such environments.

  • Mixed Flowing Gas Test Procedures for Creep Corrosion and How To Minimize Its Occurrence
    Barry S.Hindin, Ph.D., P.E., Battelle Columbus Operations
  • PCB Creep Corrosion and Board Design Considerations
    He Jingqiang, Gao Feng, Tu Yunhua, and Liu Sang, Huawei Technologies Co., Ltd.
  • Silver Corrosion in High Sulfur Environments
    James S. Tonge, Dow Corning Corporation



    WEDNESDAY, OCTOBER 27
    10:30am – 12:00pm


     AAT5 Effect of PCB Surface Finish on Lead-Free Solder Joint Reliability
    Chair: Pradeep Lall, Ph.D., Auburn University
    Co-Chair: Denis Jean, Plexus Corporation
    Wednesday, October 27, 10:30am – 12:00pm, Asia 1

    The session focuses on the printed circuit board finish interactions with lead free solder interconnects. Transition to lead-free solders has been accompanied with the proliferation of PCB surface finishes including: Electroless Nickel and Immersion Gold (ENIG), Organic Solderability Preservative (OSP), Immerse Silver (ImAg) and Immerse Tin (ImSn). The three papers in this session present findings on the effect of change in surface finish on lead-free solder joint reliability. In the first paper, the failure modes of brittle fracture and black pad have been studied in lead-free solder interconnects. In the second paper, the shear strength and random vibration response of Sn3.0Ag0.5Cu solder joints with four surface finishes, including Electroless Nickel and Immersion Gold (ENIG), Organic Solderability Preservative (OSP), Immerse Silver (ImAg) and Immerse Tin (ImSn) have been studied after 125C isothermal aging. In the third paper, the effect of multiple reflows on the reliability of low-silver lead-free interconnects is been presented.

  • Process Development and Reliability Study With Anistropic Conductive Film Bonding with Multiple Types of PCB Surface Finishes
    Jenson Lee, David Geiger, and DongkaiShangguan, Ph.D., Flextronics International
  • Effect of PCB Surface Finishes on Lead-Free Solder Joint Reliability
    Xu Zheng, Hongfeng Ran, Lei Wang, Hao Kou, Yexiang Ning, Bei Wang, and Zuyao Liu, Shenzhen Kaifa Technology Co., Ltd.
  • Effect of Multiple Reflow Cycles on Solder Joint Formation and Reliability
    Ranjit Pandher, Cookson Electronics; Ashok Pachamuthu, Cookson Electronics and Binghamton University



    SMT5 Reflow and Soldering Technologies
    Chair: Tom Zanatta, Motorola
    Co-Chair: Derek Daily, Senju Comtek Corporation
    Wednesday, October 27 10:30am – 12:00pm, Asia 2

    Three practical presentations will review current technology and new methods of reflow processes, soldering technologies and development of standardized assembly and test methods for new material evaluations. This session will cover the challenges of moving reflow recipes to new locations without developing new profiles for each assembly. We will also review an innovative approach for minimizing defects during the reflow process by carefully introducing forced oscillation.

  • A Standardized Method to Evaluate Process Material Compatibility With In-Circuit Test in High Complexity Assembly
    John McMahon, P.E., Simin Bagheri, and Lynn Klev, Celestica Inc.
  • Supporting Component Self-Alignment by Forced Oscillation During Reflow Soldering
    Florian Schüßler, Michael Pfeffer, Stefan Härter, and Jörg Franke; University Erlangen-Nuremberg
  • Experiences in Transferring Recipes from an Eight Zone Reflow Oven to a Ten Zone Oven- Unexpected Savings
    Fred Dimock, BTU International, Inc.



    MFX5 Head-in-Pillow Component Soldering Defects
    Chair: Jasbir Bath, Bath Technical Consultancy
    Co-Chair: Chrys Shea, Shea Engineering Services
    Wednesday, October 27, 10:30am – 12:00pm, Oceanic 3

    Head-in-Pillow component soldering defects are a growing problem in the industry typically related to component and/or board warpage. There are increasing developments of solder paste to help mitigate the effect. The session will discuss test methodologies to create and quantify Head-in-Pillow defects as well as potential material/ process solutions to minimize them. Results will be discussed on the redesign of components to control warpage during reflow. Information on developing iNEMI projects on qualification requirements and primary factors affecting component warpage during reflow will be presented in relation to the JEDEC standard.

  • A Procedure to Determine Head-in-Pillow Defect and Analysis of Contributing Factors
    Ranjit Pandher, Rahul Raut, Michael Liberatore, Navendra Jodhan, and Karen Tellefsen, Cookson Electronics
  • Testing and Prevention of Head-In-Pillow
    Yan Liu, Ph.D., Pamela Fiacco, M.S., and Ning-Cheng LeeSpeaker of Distinction, Ph.D., Indium Corporation
  • Effects of Component Warpage on Board Assembly Defects and Effective Mitigation Measures
    Peng Su and Guhan Subbarayan, Cisco Systems, Inc.



    PRC2 Strategies for Optimizing AOI and X-Ray Inspection
    Chair: Tim Kruse, Plexus Corporation
    Co-Chair: Peter Biocca, ITW Kester
    Wednesday, October 27, 10:30am – 12:00pm, Europe 1

    With increasing PCBA density and package complexity, reliance on AOI and X-Ray inspection to enable PCBA quality continues to grow. Strategies for optimal AOI and X-Ray application are necessary to ensure defects are detected at the most opportunistic time with the smallest cost impact and defect escape risk. Real world users outline strategies and studies that show how to minimize defect escapes while balancing efficient utilization of inspection equipment.

  • Real Life X-Ray Inspection for BGAs, QFNs, Counterfeit Components and 3D Packages
    Evstatin Krastev and David BernardSpeaker of Distinction, Nordson DAGE
  • Zero-defect Strategies With Combined Optical and X-Ray Inspection (AOI/AXI)
    Carsten Salewski and Jesper Lykke, Viscom, Inc.
  • How to Implement Good Test Coverage and Eliminate Escapes for Printed Circuits Board Assembly Operation
    Gaosen Li, An Qi Zhao, Andrew Ho, Wei Wen, Zhen (Jane) Feng, Ph. D., Murad Kurwa, FLEXTRONICS International Inc.; Haolee Yang and Liang Chen, Test Research Inc.



    SUB2 The Reliability of High Density Interconnection (HDI) PCBs for Complex Electronics
    Chair: John Davignon, Intel Corporation
    Co-Chair: Matthew Seal, Tektronix
    Wednesday, October 27, 10:30am – 12:00pm, Oceanic 5

    Although HDI has been around for several years now, there are still innovations in materials, chemistries and questions on reliability still abound. Miniaturization requires finer lines/traces while maintaining or improving signal integrity. This session will explore some of the reliability and performance improvements possible with HDI. Sexton: remove yellow.

  • Reliability Issues Caused by Bending HDI Flexible Circuits
    John Dzarnoski and Kexia Sun, Starkey Laboratories
  • Use of Non Etching Adhesion Promoters in Advanced PCB Applications
    Roger Massey and Adrian Zee, Atotech Deutschland GmbH
  • New Copper Electrolytes for Blind Microvia Filling
    Michael Dietterle, Ph.D., Dr.-Ing. Max Schlötter GmbH & Co. KG



    WEDNESDAY, OCTOBER 27
    2:00pm – 3:30pm


     AAT6 BGA Reliability Issues and Evaluation Techniques
    Chair: Marie Cole, IBM Corporation
    Co-Chair: Scott Buttars, Intel Corporation
    Wednesday, October 27, 2:00pm – 3:30pm, Asia 1

    Gain insight from this session into a variety of assembly reliability concerns affecting system field performance. Learn about new models to estimate the failure progression and residual life in drop and vibration testing. Hear recent data showing the significance of void location on interconnect fatigue reliability. Discover a technique for evaluating the thermo-mechanical reliability of the thermal interface material and cooling hardware in a high power application.

  • Residual-Life Estimation of Lead-Free Electronics in Shock and Vibration Using Kalman Filter Models
    Pradeep Lall and Ryan Lowe, Auburn University; Kai Goebel, NASA Ames Research Center
  • The Influence of Solder Void Location on BGA Thermal Fatigue Life
    Richard CoyleSpeaker of Distinction, Peter Read, Richard Popowich, Alcatel-Lucent; Heather McCormickSpeaker of Distinction, Celestica Inc.; John Osenbach, LSI Corporation
  • Evaluation of Thermal Interface Material Performance in a Cyclic Strain Environment
    Joe Doman, Eddie Kobeda, Ph.D., Jim Bielick, Joe Kuczynski, Tim Tofil, and Mike Vaughn, IBM Corporation



    SMT6 Solving Solder Voiding and Other Solder Problems
    Chair: Laura Turbini, Ph.D., Research In Motion
    Co-Chair: Dan Baldwin, Ph.D., Engent, Inc.
    Wednesday, October 27, 2:00pm – 3:30pm, Asia 2

    Solder voiding is a problem that has become increasingly an area of concern for electronic products. Since one function of the solder on a "quad flat no lead package" (QFN) is to transfer heat away from a power device, the presence of a large amount of voiding can be problematic and can lead to early device failure. Many factors can affect solder void formation including solder flux, alloy, reflow profile and board finish. Another solder problem of concern to some is the use of pin-in-paste (PIP) for a single through-hole component on an otherwise total SMT assembly. Often if sufficient solder is present or, if excess solder paste is used, flux residues can inhibit electrical probe testing. This session will address these issue and present some potential solutions.

  • Four Ways to Reduce Voids in BGA/CSP Package to Substrate Connections
    Michael A. Previti, Mitch Holtzer, and Tom Hunsinger, Cookson Electronics
  • An Investigation Into the Development of Tin-Lead and Lead-Free Solder Pastes to Reduce Voiding in Large Contact Area Power Transistor/QFN Type Components
    Jasbir BathSpeaker of Distinction, Manabu Itoh, Gordon Clark, Noriyoshi Uchida, and Hajime Takahashi, Koki Company Limited; Jasbir BathSpeaker of Distinction and Roberto Garcia, Christopher Associates Inc.
  • Applications of Solder Fortification with Preforms
    Carol Gowans and Ronald Lasky, Ph.D., P.E.Speaker of Distinction, Indium Corporation and Dartmouth College



    MFX6 Solar Module Manufacturing
    Chair: Chrys Shea, Shea Engineering Services
    Co-Chair: Irene Sterian, Celestica Inc.
    Wednesday, October 27, 2:00pm – 3:30pm, Oceanic 3

    As the manufacturing of solar modules and related electronics expands to meet increasing market demands, the needs to reduce cost, boost throughput and improve reliability become more pronounced. The solar energy market is expected to grow as rapidly as the SMT market did in the 1980's and 1990's. Many of the scientific tools and techniques that brought SMT to its current level of technology can also be applied to the solar manufacturing arena.

  • SMT Challenges in Alternative Energy
    Alan Rae, Global Solar Technology and iNEMI Inc.
  • Fabrication of Low Cost Flexible Solar Cells Using Solution-Based Coating Techniques
    Joseph Weiss, Peter Kariuki, Jasper Chiguma, Jessica Gendron, Babak Arfaei, Peter Borgesen, and Wayne Jones; Binghamton University



    SUB3 Latest Developments in Surface Finishes
    Chair: Jim Kenny, Enthone Inc., A business of Cookson Electronics
    Co-Chair: Steve Vandervoort, Intel Corporation
    Wednesday, October 27, 2:00pm – 3:30pm, Oceanic 5

    Picking the right Surface Finish for your application can be a challenge. Please join this session to understand the impact of surface finishes on your total assembly cost. Learn about the latest new finishes under development which can improve total cost and reliability.

  • Considerations for Selecting a Printed Circuit Board Surface Finish
    Randy Schueller, Ph.D.Speaker of Distinction, DfR Solutions
  • A New Surface Finish for the Electronics Industry
    Ernest Long, Ph.D., and Lenora ToscanoSpeaker of Distinction, MacDermid
  • Latest Developments in Surface Finishing of PCBs Using Plasma Deposition
    Tim von Werne, Ph.D.Speaker of Distinction, Andy Brooks, and Siobhan Woollard, Semblant Ltd.



    PRC3 Risk Mitigation for Counterfeit Electronic Components
    Chair: David Steele, Da-Tech Corporation
    Co-Chair: Anne Poncheri, Silicon Cert Laboratories
    Wednesday, October 27, 2:00pm – 3:30pm, Europe 1

    Counterfeit components in the electronics industry have become a serious threat to our economy and our safety. Reported instances of counterfeit components have dramatically increased and this trend is expected to continue. Continuing to specify the use of electronic components that are obsolete or "hard to get" are major drivers that make counterfeiting lucrative. Session presentations will provide details of the counterfeiting problem, industry responses, and risk mitigation practices.

  • Methods Used in the Detection of Counterfeit Electronic Components
    Harold "Woody" Hewett, Electro-Comp Services, Inc.
  • Using X-Ray Systems to Detect Counterfeit and Reworked Electronic Components
    Art Ogg, World Micro
  • Counterfeit Components – The 800 Pound Gorilla
    Mark Pasdon, Independent Distributors of Electronics Association



    WEDNESDAY, OCTOBER 27
    4:00pm – 5:30pm


     AAT7 Interconnection Reliability Under Drop/Shock and Vibration Loading
    Chair: Richard Coyle, Ph.D., Alcatel-Lucent
    Co-Chair: Brian Roggeman, Universal Instruments
    Wednesday, October 27, 4:00pm – 5:30pm, Asia 1

    The increasing requirements for product design and functionality, coupled with the transition to Pb-free manufacturing, have presented challenges on product reliability and manufacturing quality that are specific to Pb -ree solders. Among those challenges are the need to assess mechanical test requirements and acceptance criteria for drop/shock and vibration and the ability to develop models for crack propagation specific to Pb free solders in these test environments.

  • Evaluation of Defects in Lead-Free BGA Solder Joints Under Random Vibration Stress
    Anurag Bansal, Kuo-Chuan Liu, and Jie Xue, Cisco Systems, Inc.
  • Next Generation Board Level Underfill (BLUF) for Fine Pitch BGA and POP
    Siang Miang Yeo, Cheng Siew Tay, Ching Ching Chong, and Jin Siang Beh, Intel Corporation 
  • Survivability Assessment of Advanced Interconnects and Lead-Free Electronics Subjected to Shock and Vibration with XFEM and CZM
    Pradeep Lall, Mandar Kulkarni, and Arjun Angral, Auburn University



    SUB4 Palladium Containing Surface Finish
    Chair: Raiyo Aspandiar, Ph.D., Intel Corporation
    Co-Chair: Robert Kinyanjui, Ph.D., Sanmina-SCI Corporation
    Wednesday, October 27, 4:00pm – 5:30pm, Oceanic 5

    Palladium containing surface finishes, such as ENEPIG (Electroless Nickel-Electroless Palladium-Immersion Gold) has been gaining in popularity due to their better reliability, lower cost, wider processing windows during plating, and compatibility with wire bonding. Papers in this session will describe new developments in plating processes and metallurgical structures of palladium surface finishes and their evaluations for use in wire bonding and surface mount soldering.

  • Electroless Palladium as a PCB Surface Finish – "The Re-introduction"
    Jim Trainor, OMG Electronic Chemicals
  • The Benefits of ENEPIG with Pure Pd for Gold Wire Bonding
    Mustafa Özkök, Gustavo Ramos, and Dieter Metzger, Atotech Deutschland GmbH; Hugh Roberts, Atotech USA Inc.
  • A Study of the ENEPIG IMC for Eutectic and LF Solders
    G. Milad, D. Gudeczauskas, G. O'Brien, and A. Gruenwald, Uyemura International Corporation



    THURSDAY, OCTOBER 28
    8:00am – 9:30am


     LF1 NASA-DoD Lead-Free Electronics Project: Overview as Well as Drop Test and Mechanical Shock Test Data
    Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Co-Chair: Thomas Woodrow, Ph.D., Boeing Company
    Thursday, October 28, 8:00am – 9:30am, Asia 1

    The NASA-DoD Lead Free Electronics Project brings together experts from electronics communities in an intensive test program that is examining the reliability of Pb-free solder interconnections. The study incorporates many of the current technical drivers in a Pb-free conversion, including the solder alloy selection, surface finish, and the impact or repair and rework on the integrity of electronic packaging and interconnections. A brief overview will be presented, which describes the tasks and deliverable of the NASA-DoD project for the attendee. Then, the technical results will be presented from two important assessments: (a) drop test performance and (b) mechanical shock environments. These individual test programs are critical to the implementation of Pb-free technology in both commercial and military electronics.

  • NASA-DoD Lead-Free Electronics Project - Overview
    Kurt Kessel, ITB, Inc. (NASA)
  • Drop Test Assessment of a Medium Complexity Assembly for High Reliability Applications
    P. Snugovsky, J. Bragg, Z. Bagheri, and M. Romansky, Celestica International Inc.; A. Ganster, Crane Division NSWC; W. Russell, Raytheon; J. P. Tucker and C. A. Handwerker, Purdue University; D. D. Fritz, SAIC
  • NASA/DoD Lead-Free Electronics Project: Mechanical Shock Test
    Thomas A. Woodrow, Ph.D.Speaker of Distinction, Boeing Research and Technology



    THURSDAY, OCTOBER 28
    10:00am – 11:30am


     LF2 NASA DoD Lead-Free Report and Update (Part 2)
    Chair: Matt Kelly, P. Eng., MBA, IBM Corporation
    Co-Chair: Paul Vianco, Ph.D., Sandia National Laboratories
    Thursday, October 28, 10:00am – 11:30am, Asia 1

    As commercial electronic hardware supply chains continue to migrate towards supporting lead-free printed circuit board assembly, this shift continues to apply supply chain pressure and technical risk to mission critical, high complexity, high reliability systems currently exercising various exemptions. Reliability assessment of hardware systems operating in ruggedized, harsh environment, avionic, and space applications is of critical importance. Part 2 of the NASA DoD lead-free update will report on resulting thermomechanical reliability performance studies of these high reliability systems. This is an excellent opportunity to learn more about NASA's lead-free assembly / test experience and application requirements.

  • NASA-DoD Combined Environments Testing Results
    Cynthia Garcia, Raytheon Company
  • NASA-DoD Lead-Free Electronics Project: Vibration Test
    Thomas A. Woodrow, Ph.D.Speaker of Distinction, Boeing Research and Technology
  • NASA DoD -55°C to +125°C Thermal Cycle Test Results
    Dave HillmanSpeaker of Distinction, Tim Pearson, and Ross Wilcoxon, Rockwell Collins



    THURSDAY, OCTOBER 28
    1:00pm – 2:30pm


     LF3 The Impact of Lead-Free Materials and Soldering Processes on Printed Wiring Assemblies
    Chair: Dave Hillman, Rockwell Collins
    Co-Chair: Gus Rinella, Research In Motion
    Thursday, October 28, 1:00pm – 2:30pm, Asia 1

    The impact of the European Union's RoHS legislation on the electronics industry's material and process selection processes for printed wiring assembly manufacture has been profound. Maintaining a balance of characterized laminate materials, understood printed wiring board/component surface finishes and capable equipment technologies for the production of large, high complex electronic products is a significant task. The three papers in this session demonstrate the due diligence and document the challenges of manufacturing electronic products in a lead-free solder process environment.

  • Lead-Free HASL: Balancing Benefits and Risks for High Complexity High Reliability Server and Storage Hardware
    Matthew KellySpeaker of Distinction, Jeffrey Taylor, Brett Krull, Marie ColeSpeaker of Distinction, and Tom Truman, IBM Corporation
  • Mechanical Failures in Pb-Free Processing: Selected Mitigation Techniques for Pad Crater Defects
    Brian Gray, P. Eng., and John McMahon, P. Eng., Celestica Inc.
  • High Complexity Lead-Free Wave and Rework: The Effects of Material, Process and Board Design on Barrel Fill
    Craig HamiltonSpeaker of Distinction, John McMahon, Jose Traya, Wang Yong Kang, and Khoo Kok Wei, Celestica Inc.; Matthew KellySpeaker of Distinction and Marie ColeSpeaker of Distinction, IBM Corporation



    THURSDAY, OCTOBER 28
    3:00pm – 4:30pm


     LF4 Lead-Free Solder Joint Reliability: Impact of Alloy Composition, Design and Load Parameters
    Chair: Jean-Paul Clech, Ph.D., EPSI, Inc.
    Co-Chair: Kola Akinade, Ph.D., Cisco Systems
    Thursday, October 28, 3:00pm – 4:30pm, Asia 1

    Lead-free solder joint reliability is affected by solder alloy composition, process, design parameters and loading conditions. Addressing these requirements is key to the successful implementation of lead-free technology in mainstream as well as high-end product board assemblies. Speakers in this session will share their experiences and fundamental understanding of what helps make lead-free assemblies reliable.

  • Solder Joint Reliability of Pb-free Tin-Silver-Copper Ceramic Ball Grid Array (CBGA) Packages as a Function of Cooling Rate and Silver Content
    Richard CoyleSpeaker of Distinction, Peter Read, Debra Fleming, and Richard Popowich, Alcatel-Lucent; Robert Kinyanjui, Jonathon Shirey, Mulugeta Abtew, Sanmina-SCI Corporation, Iulia Muntele, formerly Sanmina-SCI Corporation; John Manock, formerly Alcatel-Lucent
  • New Developments in High-Temperature, High-Performance Lead-Free Solder Alloys
    Anton-Zoran Miric, W. C. Heraeus GmbH
  • Combinatorial Effects of Electromigration and Low Cycle Fatigue
    Christopher HuntSpeaker of Distinction, Davide Di Maio, Charles Murdock, and Owen Thomas, National Physical Laboratory




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